In this paper we present an approach for the analysis of systems of parallel communicating processes, with regard to Network-on-Chip applications. We present a method to detect communications that synchronize the program flow of two or more processes. These synchronization points set the processes into relation and allow the determination of the global timing behavior of such a system. Using th...

for providing me with an opportunity to carry out my master thesis project at the department of electrical engineering at the university. I thank him for his support and encouragement throughout the project. for his valuable suggestions and ideas regarding my project during the discussions in the PROMES meetings. I am especially grateful to Ir. Sander Stuijk, who guided me throughout the projec...

http://dx.doi.org/10.1016/j.compeleceng.2014.08.005 0045-7906/ 2014 Elsevier Ltd. All rights reserved. q Reviews processed and recommended for publication to the Editor-in-Chief by Guest Editor Dr. Masoud Daneshtalab. ⇑ Corresponding author. E-mail addresses: [email protected] (A. Demiriz), [email protected] (N. Bagherzadeh), [email protected] (O. Ozturk). Ayhan Demiriz a,⇑, Nader Bagherzad...

http://dx.doi.org/10.1016/j.compeleceng.2014.07.012 0045-7906/ 2014 Elsevier Ltd. All rights reserved. q Reviews processed and approved for publication by Editor-in-Chief Dr. Manu Malek. ⇑ Corresponding author. E-mail addresses: [email protected] (A. Abbas), [email protected] (M. Ali), [email protected] (A. Fayyaz), ankan.ghosh@ (A. Ghosh), [email protected] (A. Kalra), samee.khan@...

As technology scales down, the interconnect for on-chip global communication becomes the delay bottleneck. In order to provide well-controlled global wire delay and efficient global communication, a packet switched Network-on-Chip (NoC) architecture was proposed by different authors [1][2]. In this paper, the NoC system parameters constrained by the interconnections are studied. Predictions on ...

This is the second part of a two-part article that reviews a number of the current debates regarding raising and control constructions. The issues addressed in this part include the spectrum of related raising (e.g. possessor raising, further raising) and control (partial, split, generic, super-equi) phenomena; cross-linguistic typology, including backward and copy constructions; and their acqu...

We purposed a new Network on Chip (NoC) architecture called Hierarchical Graph. The most interesting feature of this novel architecture is its simple implementation process. Furthermore, the flexible structure of this topology makes it suitable for use in application specified chips. To benchmark the suggested architecture with existing ones, basic models of physical implementation have been ex...

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In this paper we present a novel shared buffer scheme for network on chip applications. The proposed scheme is based on a dynamically allocated multi queue self-compacting buffer. Two physical channels share the same buffer space. This in turn provides a larger available buffer space per channel. The proposed scheme has similar performance using only sixty three percent of the buffer size that ...