Network on Chip (NoC) is proposed as a promising intra-chip communication infrastructure. A simple and efficient routing scheme is important for large scale NoC to provide the required communication performance to applications with low area and power overheads. Although mesh is preferred for NoC, virtualization may lead to irregular topologies. In this paper, we propose a Convex-Based DOR (CBDO...

This paper presents design and characterization of NanoCu based ultra-fine pitch chip-to-package interconnects for microwave frequencies. Transitions are designed with this new interconnect and characterized upto 40 GHz in Packaging configurations such as Chip-on-Chip and Chip-onPackage.

This paper presents an interconnect resilient (IR) methodology with maximal interconnect fault tolerance, yield, and reliability for both single and multiple interconnect faults under stuck-at and open fault models. By exploiting multiple routes inherent in an interconnect structure, this method can tolerate faulty connections by efficiently finding alternative paths. The proposed approach is c...

Article history: Received 13 November 2013 Revised 13 January 2014 Available online 1 March 2014

This technical report describes a formalization for nursing knowledge found in the NANDA, NIC and NOC (NNN for short) standards. Data about nursing diagnoses and treatments consists of the following three NNN knowledge sources that are widely accepted and used in the field of care [1], i.e., NANDA1 containing all basic information about the diagnoses, the Nursing Interventions Classification (N...

The Multiscale Strip Construction, or in short MSC (Lerman et al., 2007), was initially proposed to identify enriched spots in ChIP-on-chip arrays. Here we extend this method to the setting of robust high-dimensional curve estimation. We establish its robustness as well as accurateness by bounding both the empirical influence function and the empirical bias of approximation at a sufficiently la...

Nanoscale CMOS technologies are posing new network on chip concepts to IC designers. However, the electronic network on chip design faces many problems like energy consumption, long delay and limited bandwidth. Hence, optical network on chip appears as a good candidate to solve these problems. The advances in nanophotonic technology make it more realistic. A new sparse mesh is proposed for opti...

Network-on-chip (NoC) is a new design paradigm for system-on-chip intraconnections in the billion-transistor era. Application specific on-chip network design is essential for NoC success in this new era. This paper presents a class of source routing switches that can be used to efficiently form arbitrary network topologies and that can be optimized for various applications. Hardware description...