Reconfigurable interconnection networks have been shown to benefit performance in distributed shared-memory multiprocessor machines. Usually, performance measurements for these networks require large numbers of slow full-system simulations, making designspace exploration a cumbersome and time-consuming task. In this paper, we present a prediction model for the performance of a reconfigurable ne...

We propose a new routing strategy for the KYKLOS II multiprocessor interconnection network which achieves minimum distance for the path between any two processors. For KYKLOS II with 2 processors, the average distance is shorter than those of previous routing strategies by approximately 2 log 2 n. The traffic density, a measure of traffic concentration, is comparable or better than previous str...

Scalable, hierarchical, all-optical WDM networks for processor interconnection in multiprocessor systems have been recently considered. The principal objective of this paper is to introduce an access protocol for this type of network which supports a distributed shared memory (DSM) environment. The objectives of the protocol are reduced averagelatency per packet, support of broadcast/multicast,...

Multistage Interconnection Networks (MIN) are used to connect processors and memories in large scale scalable multiprocessor systems. MINs have also been proposed as switching fabrics in ATM networks in the future Broadband ISDN networks. A MIN consists of several stages of small crossbar switching elements (SE). Buuers are used in the SEs to increase the throughput of the MIN and prevent inter...

The performance of a shared memory multiprocessor system with a multiple-bus interconnection network is studied in this paper. The eeect of bus and memory contention is modeled using a probabilistic model and a closed form solution for the acceptance probability of each processor is presented. It is assumed that each processor in the system has a distinct priority assigned to it and that arbitr...

Although directory-based cache coherence protocols are the best choice when designing chip multiprocessor architectures (CMPs) with tens of processor cores on chip, the memory overhead introduced by the directory structure may not scale gracefully with the number of cores. In this work, we show that a directory organization based on duplicating tags, which are distributed among the tiles of a t...

The SB-PRAM is an experimental multiprocessor architecture with a shared address space and synchronously running threads, i.e. giving the illusion to work on a PRAM. A 4-processor prototype has been completed while a 64processor prototype is under construction. We investigate the detection and handling of single bit errors occuring during transmission of packets in the interconnection network. ...

The system design of a locally connected competitive neural network for video motion detection is presented. The motion information from a sequence of image data can be determined through a two-dimensional multiprocessor array in which each processing element consists of an analog neuroprocessor. Massively parallel neurocomputing is done by compact and efficient neuroprocessors. Local data tran...