Chip-multiprocessing is considered the future path for performance enhancements in computer architecture. Eight processor cores on a single chip are state-of-the art and several hundreds of cores on a single die are expected in the near future. General purpose computing is facing the challenge how to use the many cores. However, in embedded real-time systems thread-level parallelism is naturall...

Software dynamic translation and multiprocessing hardware are both becoming prevalent in today’s computing environment. Unfortunately, many of the programs being run under software dynamic translation are single threaded, and are unable to take advantage of thread level parallelism. This work presents the groundwork for enabling the Strata software dynamic translation framework to run in multip...

Data prefetching via helper threading has been extensively investigated on Simultaneous MultiThreading (SMT) or Virtual Multi-Threading (VMT) architectures. Although reportedly large cache latency can be hidden by helper threads at runtime, most techniques rely on hardware support to reduce context switch overhead between the main thread and helper thread as well as rely on static profile feedb...

*System Devices Research Laboratories †NEC Electronics Corporation We propose several techniques of Asymmetric Multi-processing (AMP) for mobile application processors. In our AMP architecture, multiple general purpose processors are integrated on a chip to reduce hardware development period and cost. Our techniques are well considered the role of hardware and software to maximize the benefits ...

Achieving application software portability is challenging for a computer-based system that has a single embedded processor. Such portability is even more challenging when performance requirements demand distributing and parallelizing the application software to run on an embedded scalable heterogeneous multiprocessing hardware target. Application software development for such an embedded multic...

The applications of heterogeneous embedded systems for biomedical engineering are promising, as quick response is often required due to the life-saving nature engineering, and multiple devices with completely different cores designs can be involved in a single patient. In this paper, we propose multiprocessing framework then, regard framework, an architecture that uses finite state machines (FS...

PSAM consists of a number of multithreaded pipeline processors to support parallel computation. Thread control is implemented using a distributed approach, in which each processor can independently initiate and terminate a thread. This thread control mechanism is based on data ow model, and allows the degree of multiprocessing to vary with time. Although the basic processor is von Neumannbased,...

Shared-memory multiprocessing is emerging as a popular approach to increase computing power, over that of sequential computing, while maintaining programmability. What makes the base shared-memory paradigm attractive is the simplicity of the programming model: all memory is in a pool and is globally shared. Furthermore, architectures that do not require a broadcast channel for interprocessor co...

A design approach for selectivity among several traditional hardware fault tolerance methods is proposed. By basing these methods on eld-programmable gate array (FPGA) technology, resources are eeciently used. Each fault tolerance method can be applied to any subset of the redundant modules without the use of steering logic such that the structure of the method is preserved. An architecture sup...