A low-complexity VLSI array of versatile multiplier in normal basis over GF(2n) is presented. The finite field parameters can be changed according to the user’s requirement andmake themultiplier reusable in different applications. It increases the flexibility to use the same multiplier for different applications and reduces the user’s cost. The proposed multiplier has a regular structure and is...

comparing the performance of a set of activities or organizations under uncertainty environment has been performed by means of fuzzy data envelopment analysis (fdea) since the traditional dea models require accurate and precise performance data. as regards a method for dealing with uncertainty environment, many researchers have introduced dea models in fuzzy environment. some of these models ar...

This paper extends Samuelson’s theory of optimal government purchases by accounting for the contribution of government purchases to macroeconomic stabilization. Using a matching model of the macroeconomy, we derive a sufficient-statistics formula for optimal government purchases. The formula implies that the deviation of optimal government purchases from the Samuelson level is proportional to t...

In this paper, the authors have compared the efficiency of the Karatsuba multiplier using polynomial multiplication with the multiplier implementing Vedic mathematics formulae (sutras), specifically the Nikhilam sutra. The multipliers have been implemented using Spartan 2 xc2s200 pq208 FPGA device having speed grade of -6. The proposed Karatsuba multiplier has been found to have better efficien...

A novel CMOS monolithic analog multiplier capable of operating in two quadrants is described in this thesis. The multiplier incorporates a voltage-controlled variable linear resistor comprised of two FET transistors in the feedback network of an operational amplifier. This novel approach to implementing an analog multiplier results in good linearity and wide input dynamic range when compared to...

Representing finite field elements with respect to the polynomial (or standard) basis, we consider a bit parallel multiplier architecture for the finite field GF (2). Time and space complexities of such a multiplier heavily depend on the field defining irreducible polynomials. Based on a number of important classes of irreducible polynomials, we give exact complexity analyses of the multiplier ...

Presently, the design of a compact multiplier is playing a vital role in the stream of VLSI signal processing, DSP, Modern wireless communication etc. The main goal of this proposal is to design a compact booth multiplier by using modified radix4 recoding and an efficient finite state machine (FSM) to achieve small chip size and low delay utilization. In the existing technique, compression base...

This paper proposes a reconfigurable pipelined multiplier architecture that achieves high performance and very low energy dissipation by adapting its structure to computational requirements over time. In this reconfigurable multiplier, energy is saved by disabling and bypassing an appropriate number of pipeline stages whenever input data rates are low. To evaluate the efficiency of our multipli...

This paper presents a well-structured modified Booth encoding (MBE) multiplier which is applied in the design of a reconfigurable multiply-accumulator (MAC) core. The multiplier adopts an improved Booth encoder and selector to achieve an extra-row-removal and uses a hybrid approach in the two’s complementation circuit to reduce the area and improve the speed. The multiplier is used to form a 32...

In this paper, a new architecture for MOS Current Mode Logic (MCML) array multiplier for mixed-signal applications is proposed. The proposed architecture employs active shunt-peaking technique in conventional MCML circuits. The technique of active shunt-peaking offers a way for increasing the speed of MCML gates. The performance of the proposed MCML array multiplier is compared with the convent...