نتایج جستجو برای: microarchitecture
تعداد نتایج: 12084 فیلتر نتایج به سال:
As the instruction issue width of superscalar processors increases, instruction fetch bandwidth requirements will also increase. It will eventually become necessary to fetch multiple basic blocks per clock cycle. Conventional instruction caches hinder this effort because long instruction sequences are not always in contiguous cache locations. Trace caches overcome this limitation by caching tra...
Collagen XI alpha 1 (Col11a1) is an extracellular matrix molecule required for embryonic development with a role in both nucleating the formation of fibrils and regulating the diameter of heterotypic fibrils during collagen fibrillar assembly. Although found in many different tissues throughout the vertebrate body, Col11a1 plays an essential role in endochondral ossification. To further underst...
Multithreaded (MT) processors reduce the waste of issue width by executing instructions from multiple threads at the same time. On the other hand, out-of-order commit (OOC) processors have been recently proposed as an efficient way of avoiding pipeline stalls when a long-latency instruction reaches the commit stage. In this work, we analyze the impact on performance of combining both MT and OOC...
As a promising nonvolatile memory technology, Phase Change Memory (PCM) has many advantages over traditional DRAM. Multilevel Cell PCM (MLC) has the benefit of increased memory capacity with low fabrication cost. Due to high per-cell write power and long write latency, MLC PCM requires careful power management to ensure write reliability. Unfortunately, existing power management schemes applied...
With the introduction of the high-frequency IBM System z10e processor design, a new, robust cache hierarchy was needed to enable up to 80 of these processors aggregated into a tightly coupled symmetric multiprocessor (SMP) system to reach their performance potential. Typically, each time the processor frequency increases by a significant factor, as did the z10e processor over the predecessor IB...
This thesis explores a new approach to building data-parallel accelerators that is based on simplifying the instruction set, microarchitecture, and programming methodology for a vector-thread architecture. The thesis begins by categorizing regular and irregular data-level parallelism (DLP), before presenting several architectural design patterns for data-parallel accelerators including the mult...
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