This paper describes a performance examination of the DDR2 DRAM architecture and the proposed cache-enhanced variants. These preliminary studies are based upon ongoing collaboration between the authors and the Joint Electronic Device Engineering Council (JEDEC) Low Latency DRAM Working Group, a working group within the JEDEC 42.3 Future DRAM Task Group. This Task Group is responsible for develo...

Network on chip (NoC) is an integrated communication system (SoC), efficiently connecting various intellectual property (IP) modules a single die. NoC has been suggested as enormously scalable solution to overcome the problems in SoC. The performance of depends several aspects terms area, latency, throughput, and power. In this paper, 2D 3D mesh Virtex-5 field-programmable gate array (FPGA) stu...

Network emulation offers a flexible solution for network deployment and operations, leveraging software to consolidate all nodes in topology utilizing the resources of single host system server. This research paper investigated state cybersecurity virtualized systems, covering vulnerabilities, exploitation techniques, remediation methods, strategies, based on an extensive review related literat...

Recent research has shown that Network on-chip (NoC) is superior to a bus in terms of power and area for given traffic throughput requirements. Consequently, NoC is expected to be the main interconnect infrastructure in future System on Chip (SoC) and chip multi-processor (CMP). Unlike off-chip networks, VLSI modules are only a few millimeters apart, hence the cost of off-network communication ...

Technology makes it easier for us to communicate over a distance. However, there are still many remote areas that find difficult communicate. This is due the fact communication infrastructure in some expensive build while profit will be low. paper proposes combine voice internet protocol (VoIP) mesh network implemented on openWRT router. The routers performing functions. We set up VoIP server r...

Recent research has shown that Network on-chip (NoC) is superior to a bus in terms of power and area for given traffic throughput requirements. Consequently, NoC is expected to be the main interconnect infrastructure in future System on Chip (SoC) and chip multi-processor (CMP). Unlike off-chip networks, VLSI modules are only a few millimeters apart, hence the cost of off-network communication ...

With the rapid new advancements in technology, there is an enormous increase devices and their versatile need for services. Fifth-generation (5G) cellular networks (5G-CNs) with network slicing (NS) have emerged as a necessity future mobile communication. The available partitioned logically into multiple virtual to provide range of users’ specific Efficient resource allocation methods are criti...

In this paper, a generic asynchronous First In First Out (FIFO) based WISHBONE compatible plug and play Network Interface (NI) for Network on Chip (NoC) is designed and verified. Four different types of encoded asynchronous FIFOs namely binary, Gray, one-hot and Johnson are designed and analyzed. It is found that Gray-code asynchronous FIFO is the best to handle the asynchronous clock domain is...

In the emerging high-speed packet-switched networks, fair packet scheduling algorithms in switches and routers will form an important component of the mechanisms that seek to satisfy the Quality of Service (QoS) requirements of various applications. The latency bound of a scheduling discipline is an important QoS parameter, especially for real-time playback applications. Frame-based schedulers ...