Direct tunneling current through the gate oxide is becoming a significant component of transistor leakage in deep sub-micron technology. This paper studies how gate leakage impacts the performance of analog CMOS ICs for the 90nm node. Results show that in DC referencing circuits such as current mirrors, a tradeoff exists between transistor width and mirrored reference current to improve accurac...

A voltage scalable 0.26 V, 64 kb 8T SRAM with 512 cells per bitline is implemented in a 130 nm CMOS process. Utilization of the reverse short channel effect in a SRAM cell design improves cell write margin and read performance without the aid of peripheral circuits. A marginal bitline leakage compensation (MBLC) scheme compensates for the bitline leakage current which becomes comparable to a re...

This paper describes a CMOS analogy voltage supper buffer designed to have extremely low static current Consumption as well as high current drive capability. A new technique is used to reduce the leakage power of class-AB CMOS buffer circuits without affecting dynamic power dissipation. The name of applied technique is TRANSISTOR GATING TECHNIQUE, which gives the high speed buffer with the redu...

Leakage current promises to be a major contributor to power dissipation in future technologies. Bounding the maximum and minimum leakage current poses an important problem. Determining the maximum leakage ensures that the chip meets power dissipation constraints. Applying an input pattern that minimizes leakage allows extending battery life when the circuit is in stand-by mode. Finding such vec...

In this paper, the impact of gate induced drain leakage (GIDL) on the overall leakage of submicrometer VLSI circuits is studied. GIDL constitutes a serious constraint, with regards to off-state current, in scaled down complimentary metal–oxide–semiconductor (CMOS) devices for DRAM and/or EEPROM applications. Our research shows that the GIDL current is also a serious problem in scaled CMOS digit...

In this paper, the impact of gate induced drain leakage (GIDL) on overall leakage of submicron VLSI circuits is studied. GIDL constitutes a serious constraint, with regards to off-state current, in scaled down CMOS devices for DRAM and/or EEPROM applications. Our research shows that the GIDL current is also a serious problem in scaled CMOS digital VLSI circuits. We present the experimental and ...

The characteristics of the reverse leakage current of GaInN/GaN multiple quantum well light-emitting diodes (LEDs) are examined with various n-type GaN doping concentrations and interpreted by using a tunnelling current model. Changing the doping concentration of the n-type GaN influences the tunnelling probability of electrons into the conduction band and thus the reverse leakage current. Redu...

Internet of things(IoT) development tends to reduce the reliance on centralized servers. The zero-trust distributed system combined with blockchain technology has become a hot topic in IoT research. However, distribution data storage services and different protocols make network interoperability cross-platform more complex. Relay chain is promising cross-chain that solves complexity compatibili...

This paper proposes a new single phase transformerless Photovoltaic (PV) inverter for grid connected systems. It consists of six power switches, two diodes, one capacitor and filter at the output stage. The neutral of the grid is directly connected to the negative terminal of the source. This results in constant common mode voltage and zero leakage current. Model Predictive Controller (MPC) tec...