Networks of workstations are becoming a popular platform for parallel computing. Asynchronous Transfer Mode (ATM) network connections can improve the communication characteristics of these parallel clusters. This paper introduces a new class of topologies for constructing multicomputers called Small ATM Switch based Interconnection Networks (SASIN). The Round Table Network (one kind of SASIN) i...

Dual core microprocessors are currently available and higher processor-count architectures will dominate the multicore market. A complex part of these higher order multicore designs will be the interconnection scheme that exists onchip and how exactly that interconnection is best used and configured. While FPGAs currently support a variety of onchip bus interconnects, there is a gap in the tool...

On-chip interconnection networks or Network-onChips (NoCs) are becoming the de-facto scaling communication techniques in Multi-Processor System-on-Chip (MPSoC) or Chip Multiprocessor (CMP) environment. However, the current traffic models for on-chip interconnection networks are insufficient to capture the traffic characteristics as well as evaluate the network performance. As the technology sca...

Computer architects have realized that interconnection bandwidth has become a critical limitation to the development of highperformance multiprocessor systems. Major reason is that the progress of processor performance has increasingly outpaced that of the interconnection networks, thereby limiting the usefulness of multiprocessor systems. This work presents a comprehensive study and the develo...

Owing to its nice properties, the pancake is one of the Cayley graphs that were proposed as alternatives to the hypercube for interconnecting processors in parallel computers. In this paper, we present embeddings of rings, grids and hypercubes into the pancake with constant dilation and congestion. We also extend the results to similar efficient embeddings into the star graph.

In this paper, we consider a highly recursive interconnection network known as the fully connected cubic network (FCCN). By exploiting its recursive properties, we thoroughly analyze the performance of a simple routing algorithm for the FCCN. We show that at least 800 of the routes obtained from this simple algorithm are shortest paths, and this percentage increases further with the network siz...

Status of this Memo This memo provides information for the Internet community. It does not specify an Internet standard. Distribution of this memo is unlimited. Abstract This memo discusses and defines a number of terms that are used in describing performance benchmarking tests and the results of such tests. The terms defined in this memo will be used in additional memos to define specific benc...

In this thesis, a scalable interconnection architecture for many-core systems is proposed and the tradeoffs in the design of this architecture are described. Using this model we investigate how the other aspects of network architecture like routing strategy, routing algorithms, buffer space and traffic pattern impact the performance of interconnection network. This report also discusses the sim...

Most reconngurable multi-fpga architectures have a programmable interconnection network that can be reconngured to implement diierent interconnection patterns between the fpgas and memory devices on the board. Partitioning tools for such architectures must produce the necessary pin-assignments and interconnect connguration stream that correctly implement the partitioned design. We call this pro...

Cluster computing provides an economical alternative for high performance computing, that in the past could only be provided by expensive parallel supercomputers. Clusters are built with standard components and interconnected by various interconnection topologies. These interconnection topologies provide different approaches for communication between processing nodes within the cluster. A study...