In this paper, we introduce a memory and cache contention denial-of-service attack its hardware-based countermeasure. Our can significantly degrade the performance of benign programs by hindering shared resource accesses programs. It be achieved simple C-based malicious code while degrading 47.6% on average. As another side-effect, our also leads to greater energy consumption system 2.1× averag...

During system call execution, it is common for operating system kernels to read userspace memory multiple times (multi-reads). A critical bug may exist if the fetched userspace memory is subject to change across these reads, i.e., a race condition, which is known as a double-fetch bug. Prior works have attempted to detect these bugs both statically and dynamically. However, due to their imprope...

The paper presents an indirect method to automatically prove liveness for pipelined microprocessors. This is done by first proving safety—correctness for one step, starting from an arbitrary initial state that is possibly restricted by invariant constraints. By induction, the implementation will be correct for any number of steps; we need to prove that for some fixed number of steps, n, the imp...

We describe an approach and set of tools for quantifying the potential error introduced by not simulating instructions from mispredicted paths in out-of-order speculative superscalar processors. The approach consists of modeling the behavior of programs on out-of-order superscalar processors twice: once by actually simulating the effects of the instructions in the mispredicted paths, and once b...

This paper discusses the design and implementation of the ARMSim, a simulator implemented in the Java and C programming languages for the Advanced RISC Machine (ARM) processor. The intended users of this tool are those individuals interested in learning computer architecture, particularly those with an interest in the Advanced RISC Machine processor family. ARMSim facilitates the learning of co...

Deeply pipelined high performance processors require highly accurate branch prediction to drive their instruction fetch. However there remains a class of events which are not easily predictable by standard two level predictors. One such event is loop termination. In deeply nested loops, loop terminations can account for a significant amount of the mispredictions. We propose two techniques for d...

Many hardware primitives have been proposed for synchronization and atomic memory update on shared-memory multiprocessors. In this paper, we focus on general-purpose primitives that have proven popular on small-scale bus-based machines, but have yet to become widely available on large-scale, distributed-memory machines. Specifically , we propose several alternative implementations of fetch and ...

In this paper we present a technique for fast approximately timed simulation of software within a virtual prototyping framework. Our method performs a static analysis of the program control flow graph to construct annotations of the simulated program, combined with dynamic performance information. The static analysis estimates execution time based on a target architecture model. The delays intr...

Branch target buffers (BTBs) are caches in which branch information is stored that is used for branch prediction by the fetch stage of the instruction pipeline. A typical BTB requires a few kbyte of storage which makes it rather large and, because it is accessed every cycle, rather power consuming. Partial resolution has in the past been proposed to reduce the size of a BTB. A partial resolutio...