We observe that the same SRAM cell leaks differently, under withindie process variations, when storing 0 and 1; this difference can be up to 3 orders of magnitude (averaging 57%) at 60mv variation of threshold voltage (Vth). Thus, leakage can be reduced if most often the values with less leakage are stored in the cache SRAM cells. We show applicability of this proposal by presenting three binar...

Branches interrupt the sequential flow of instructions and introduce pipeline bubbles. Branch penalty can be a significant component of effective cpi (cycles per instruction) in multiple instruction issue processors. Two key issues need to be resolved to alleviate this problem: a branch resolution scheme to decide the direction and target of a branch early in the pipeline, thus allowing target ...

The hit ratio of the first level cache is one of the most important factors in determining the performance of embedded computer systems. Prefetching from lower level memory structure is one of the techniques for improving the hit ratio of the first level cache. This paper proposes an effective prefetch scheme for the first level instruction cache by exploiting cache history information. The pro...

Inability to reuse data, conflicting references, and underutilization of cache capacity are responsible for poor cache performance on various commonly used applications. Data prefetching, blocking, and data copying have been used to address these problems. These techniques, though effective, are directed towards solving one aspect of the overall problem. We propose a comprehensive solution to t...

Two component architectures for MIN-connected multiprocessors: the Piled Banyan Switching Fabrics (PBSF) and MINC (MIN with Cache consistency mechanism) are evaluated with a real machine SNAIL-2 and an instruction level simulator. The PBSF is a high bandwidth MIN with three dimensional structure, and the MINC is a mechanism for controlling the consistency of private cache modules provided betwe...

We improve instruction cache data analysis techniques with a framework based on vector quantization and hidden Markov models. As a result, we are capable of carrying out efficient automated attacks using live I-cache timing data. Using this analysis technique, we run an I-cache attack on OpenSSL’s DSA implementation and recover keys using lattice methods. Previous I-cache attacks were proof-of-...

Advancements in multi-core have created interest among many research groups in finding out ways to harness the true power of processor cores. Recent research suggests that on-board component such as cache memory plays a crucial role in deciding the performance of multi-core systems. In this paper, performance of cache memory is evaluated through the parameters such as cache access time, miss ra...

In most modern processor designs the L1 data cache has become a major consumer of power due to its increasing size and high frequency access rate. In order to reduce this power consumption, we propose in this paper a straightforward filtering technique. The mechanism is based on a highly accurate forwarding predictor that determines if a load instruction will take its corresponding data via for...

We investigate the e ect that caches have on the performance of sorting algorithms both experimentally and analytically. To address the performance problems that high cache miss penalties introduce we restructure heapsort, mergesort and quicksort in order to improve their cache locality. For all three algorithms the improvement in cache performance leads to a reduction in total execution time. ...

In real-time systems, cache memory poses challenge to improve both predictability and performance because of its adaptive and dynamic behavior. Recent studies indicate that for application-specific embedded systems, static cache-locking helps determining the worst case execution time (WCET) and cache-related preemption delay. In this work, we propose a static instruction cachelocking algorithm ...