In a formalism of top-down design, we consider the decomposition of behavioral specications into interacting sequential components. The higher level of description speci es the operations to be performed in a major computation step. The goal is to incorporate a given interface speci cation in a lower-level speci cation that accounts for interactions with and among sequential components. This co...

Characteristics of the data being processed can be used to reduce the power consumption in the data path of a VLSI circuit by exploiting their relationship with transition activity during highlevel synthesis. Important relationships between fixed-point, two’s complement data characteristics and 0→1 transition activity in static CMOS circuits are presented in this paper. Models for computing tra...

This paper deals with power minimization problem for datadominated applications based on a novel concept called partially guarded computation. We divide a functional unit into two parts – MSP (Most Significant Part) and LSP (Least Significant Part) and allow the functional unit to perform only the LSP computation if the range of output data can be covered by LSP. We dynamically disable MSP comp...

High end video applications are still implemented in hardware consisting of many components. Integration of these components on one IC is di cult as they are typically low volume products and often customization is also required, e.g. in studio applications. This is easier on the board level than on an integrated system. Using hardware parameters for customization can partly overcome the exibil...

The earlier the stage where we perform low power design, the higher the dynamic power reduction we achieve. In this paper, we focus on reducing switching activity in high-level synthesis, especially, in the problem of functional module binding, bus binding or register binding. We propose an effective low power bus binding algorithm based on the table decomposition method, to reduce switching ac...

A module generator is described that allows for the generation of synthesizable VHDL modules which implement arbitrary functions in fixed point precision using the Symmetric Table Addition Method (STAM). This module generator was interfaced to a high level synthesis tool “fly” which automatically generates fully-pipelined circuits from a Perl-like language. The resulting system was applied to t...

The paper proposes a new model for veriication and high level synthesis (re)using complex units like co-processors. The model is called FSMC (FSM with Co-processors) and is an extension of the FSMD model (FSM with Data path). The veriication method is based on model checking. It permits to analyze the properties and consistency of the whole system and, particularly, the correct (re)use of desig...

Delay computation in combinational logic circuits is complicated by the existence of unsensit-izable (false) paths and this problem is arising with increasing frequency in circuits produced by high-level synthesis procedures. Various sensitization conditions have been proposed in the past to eliminate false paths in logic circuits, but we use a recently developed single-vector condition, that i...

In this paper, we propose a floorplan-aware complexity reduction methodology for digital filters. The proposed scheme integrates high-level synthesis and floorplan to obtain improvement in both computational complexity and interconnect delay. Physical information of floorplan is incorporated into architecture synthesis. By considering interconnects while synthesizing reduced-complexity filters,...

This work presents the results obtained using a methodology that allows the hardware implementation and the rapid prototyping of communication protocols. The implementation results of diierent description styles of protocols and recommendations to the use of this methodology are discussed. A comparison among the protocol implementation using the High Level Synthesis technique with standard cell...