In this paper, a novel asynchronous layered interface for a high performance on-chip bus is designed in a Globally Asynchronous Locally Synchronous (GALS) style. The proposed asynchronous layered interface with distributed and modularized control units supports multiple outstanding in-order/out-of-order transactions to achieve high performance. In the layered architecture, extension of an async...

Nowadays design paradigms of highly complex and integrated Systems-on-a-Chip (SoC) are based on the assembling of predesigned cores and components (Intellectual Property, IP cores). That way, test and development cycles —and finally the time-to-market— can be reduced. To have the manyfold components interoperate with each other in order to get the desired functionality, interconnections between...

This paper investigates the power bus noise and power bus impedance of printed circuit boards with four different kinds of embedded capacitance. These boards have power-ground plane pairs separated by a very thin layer of material with high dielectric permittivity. It is shown that embedded capacitance effectively reduces power bus noise over the entire frequency range evaluated (up to 5 GHz).

Power and ground planes on multilayer PCBs can effectively radiate electromagnetic fields excited by the IC simultaneous switching noise. The high frequency electromagnetic radiation is often calculated from the electric field along the edge of the PCB, which can be estimated with a cavity model using magnetic walls. The excitation of the cavity modes is related to the via current passing throu...

Bus-based shared memory multiprocessors with private caches and snooping write-invalidate cache coherence protocols are dominant form of smallto medium-scale parallel machines today. In these systems the high memory latency poses the major hurdle in achieving high performance. One way to cope with this problem is to use various techniques for tolerating high memory latency. Software-controlled ...

Commutation failure is a common fault for line-commutated converters in the inverter. To reduce the possibility of commutation failure, many prediction algorithms based on alternating current (AC) voltage detection have already been implemented in high voltage direct current (HVDC) control and protection systems. Nevertheless, there are currently no effective methods to prevent commutation fail...

CORBA presents a model of distributed computing in which distributed objects communicate using a high-level “information bus” called an Object Request Broker (ORB). In this paper we describe a problem with the current CORBA specification that makes ORB communication non-type-safe in certain situations. We describe a solution to the problem based on the use of unique identifiers, and show how it...

This paper presents an analysis for measuring performance of asynchronous packet switched hierarchical and multiplc-bus multiprocessor systems. T h e performance was measured using both the analytical and simulation models. The performance measured from the analytical model was found to be very close to the performance measured from the simulation model. The performance of a hierarchical bus sy...

In this paper, we proposed an high-speed and low-power off-chip data bus interface based on the best coding schemes in this hard operative condition. We analyzed the clustered bus invert method and the bus switch coding, a newly proposed approach based on bus lines logically re-ordered. We proposed an high speed and low-power bus interface based on the combined employment of these two approache...