This paper presents the designs of asynchronous early output dual-bit full adders without and with redundant logic (implicit) corresponding to homogeneous and heterogeneous delay-insensitive data encoding. For homogeneous delay-insensitive data encoding only dual-rail i.e. 1-of-2 code is used, and for heterogeneous delay-insensitive data encoding 1-of-2 and 1-of-4 codes are used. The 4-phase re...

Power consumption has emerged as a primary design constraint for integrated circuits (ICs). In the Nano meter technology regime, leakage power has become a major component of total power. Full adder is the basic functional unit of an ALU. The power consumption of a processor is lowered by lowering the power consumption of an ALU, and the power consumption of an ALU can be lowered by lowering th...

Low power design of VLSI circuits has been identified as a critical technological need in recent years due to the high demand for portable consumer electronics products. In this regard many innovative designs for basic logic functions using pass transistors and transmission gates appeared in the literature recently. But they were all designed mostly by intuition and cleverness of the designer. ...

An important arithmetic component of “Arithmetic and Logic Unit” or ALU is reconfigured in this paper, known as “Full-Adder-Subtractor”, where an advance low-power, high-speed nano technology “QCA” with electro-spin criterion used reversibility the advancement multilayer 3D circuitry. In modern digital world, selected nano-sized effective alternative widely “CMOS Technology” because all limitat...

We introduce I1 has no pairs as an antonym of I1 has a pair. Observe that every set which is empty has also no pairs. Let x be a non pair set. Observe that {x} has no pairs. Let y be a non pair set. Note that {x,y} has no pairs. Let z be a non pair set. One can verify that {x,y,z} has no pairs. Let us observe that there exists a non empty set which has no pairs. Let X , Y be sets with no pairs....

The fused floating-point three-term adder performs two additions in a single unit to achieve better performance and better accuracy compared to a network of traditional floating-point two-term adders, which is referred to as a discrete design. Here are several critical design issues for the fused floating-point three-term adder: 1) Complex exponent processing and significand alignment, 2) Compl...