Modern SoCs are getting increasingly heterogeneous with a combination of multi-core architectures and hardware accelerators to speed up the execution of computeintensive tasks at considerably lower power consumption. Modern FPGAs, due to their reasonable execution speed and comparatively lower power consumption, are strong competitors to the traditional GPU based accelerators. High-level Synthe...

Reconfigurable hardware is by far the most dominant implementation platform in terms of the number of designs per year. During the past decade, security has emerged as a premier design metrics with an ever increasing scope. Our objective is to identify and survey the most important issues related to FPGA security. Instead of insisting on comprehensiveness, we focus on a number of techniques tha...

We examine the relationship between FPGA size and software speedup when an on-chip FPGA is used to implement critical software loops through hardware/software partitioning. We studied seven benchmark programs taken from Mediabench and Netbench. We profiled the programs on the SimpleScalar architecture, rewrote the critical loops in VHDL, synthesized and mapped those loops to a Xilinx FPGA, and ...

We describe the capabilities of and algorithms used in a new FPGA CAD tool, Versatile Place and Route (VPR). In terms of minimizing routing area, VPR outperforms all published FPGA place and route tools to which we can compare. Although the algorithms used are based on previously known approaches, we present several enhancements that improve run-time and quality. We present placement and routin...

We present a FPGA-synthesizable version of the Intel Nehalem processor core, synthesized, partitioned and mapped to a multi-FPGA emulation system consisting of Xilinx Virtex4 and Virtex-5 FPGAs. To our knowledge, this is the first time a modern state-of-the-art x86 design with the out-oforder micro-architecture is made FPGA synthesizable and capable of high-speed cycle-accurate emulation. Unlik...

Authors: Prof. Dirk Stroobandt, Tom Davidson, Karel Heyse, Amit Kulkarni Venues: Copenhagen Sept. 11th; Stockholm Sept. 9th Abstract: Dynamic Circuit Specialization (DCS) is a technique used to optimize FPGA applications when some of the inputs, called parameters, are infrequently changing compared to other inputs. For every change of parameter input values, a specialized FPGA configuration is ...

This paper shows the benefits of the Field Programming Gate Array (FPGAs) in industrial control applications. The author starts by addressing the benefits of FPGA and where it is useful. As well as, the author has done some FPGA’s evaluation researches on the FPGA performing explaining the performance of the FPGA and the design tools. To show the benefits of the FPGA, an industrial application ...

The paper presents the implementation of analog data acquisition system, in particular controlling with a 6channel ADC converter AD7656 via the FPGA Xilinx Spartan 3 series. The procedures for data sending from the ADC to the FPGA buffers, their conversion and subsequent transmission to TigerSHARC DSP are described. The digital representations of ADC analog input signals are sent to the FPGA th...

In this paper, we present a high-level power modeling technique to estimate the power consumption of reconfigurable devices such as complex programmable logic devices (CPLDs) and field-programmable gate arrays (FPGAs). For simplicity of reference, we simply refer to these devices as FPGAs. First, we capture the relationship between FPGA power dissipation and I/O signal statistics. We then use a...

This new toolchain for accelerating application on CPU-FPGA platforms, called Courier-FPGA, extracts runtime information from a running target binary, and re-constructs the function call graph including input-output data. Then, it synthesizes hardware modules on the FPGA and makes software functions on CPU by using Pipeline Generator. The Pipeline Generator also builds a pipeline control progra...