In this paper a new model is proposed for Gate Oxide Short defects based on a non-split MOS transistor. Because the MOS is not split, this model allows to simulate minimum transistors in realistic digital circuits. The construction of the model is presented in details using a comprehensive and didactic approach. It is demonstrated that the electrical behavior of the proposed model perfectly mat...

We have demonstrated a room-temperature silicon single-electron transistor memory that consists of ~i! a narrow channel metal-oxide–semiconductor field-effect transistor with a width ~;10 nm! smaller than the Debye screening length of single electron; and ~ii! a nanoscale polysilicon dot ~;737 nm! as the floating gate embedded between the channel and the control gate. We have observed that stor...

In this paper, we will discuss several new reliability issues facing CMOS transistors with ultra thin gate oxides and their impacts on projection of operation voltage V10Y for 10-year lifetime. The most important findings are: 1). Oxide lifetime is more meaningfully determined by an event taking place much earlier than oxide breakdown: a strongly transistor-size dependent increment in gate leak...

The failure of the depletion approximation in the near surface region implies that conventional MOS C-V measurements yield erroneous doping profiles in that region. Integrating MOS C-V doping profiles yields only a partial dose excluding the important surface dose portion. Here, we report a new approach, which enables the determination of the entire doping dose, taking into account the crucial ...

We describe a theoretical approach to transport and a potentially valuable scheme for screening gate dielectric materials. Realistic structural models of the Si-dielectric interface are employed for Si-SiO2-Si model metal-oxide–semiconductor ~MOS! structures. The leakage current for a 1.02-nm MOS structure is calculated from first principles using Landauer’s ballistic transport approach and ab ...

A physical-based model for MOS capacitors in accumulation is presented, which is able to predict the non-linear distortion accurately. The key idea of this work is to include the polysilicon gate depletion effect in that model. Several test structures based on MOS capacitors in accumulation have been implemented with the aim of validating the model and to explore the potential applications to h...

In this paper, we present a solution to the ultra low voltage inverter by adding a keeper transistor in order to make the semi-floating-gate more stable and to reduce the current dissipation. Moreover, we also present a differential ULV inverter and elaborate on the reliability and fault tolerance of the gate. The differential ULV gate compared to both a former ULV gate and standard CMOS are gi...

In Semiconductor industry has witnessed and explosive growth of integration of sophisticated multimedia base application onto mobile electronic gadget since the last decade. The critical concern in this aspect is to reduce the power consumption beyond a certain range of operating frequency. An important factor in the design of VLSI circuits is the choices of reversible logic. Basically conventi...

Introduction: The increase of transistor speed in CMOS technologies has been reached mainly by scaling the gate length of the MOS transistors. For the most advanced technologies, gate lengths down to 40 nm with an ft of 243 GHz [1] have been reported. This allows performances comparable to expensive III-V technologies based on GaAs or InP and in addition the potential for very large scale integ...

A threshold-logic gate device consisting of subthreshold MOSFET circuits is proposed. The gate device performs threshold-logic operation, using the technique of current-mode addition and subtraction. Sample digital subsystems, i.e., adders and morphological operation cells based on threshold logic, are designed using the gate devices, and their operations are confirmed by computer simulation. T...