Detection of floating-point rounding errors normally requires run-time analysis in order to be effective and software-based tools are seldom used due to the extremely high computational demands. In this paper we present a field programmable gate array (FPGA) based floating-point coprocessor which supports standard IEEE-754 arithmetic, user selectable precision and Monte Carlo Arithmetic (MCA). ...

A new approach for implementing block-floating-point arithmetic is proposed. This approach intends to preserve the least-significantbits (LSBs) to improve signal processing quality. The preservation of LSBs is automatically and perfectly done by hardware. Several simulation results of the proposed block-floating-point implementation have shown improved SNRs over conventional blockfloating-point...

An algorithm is presented for computing verified and accurate bounds for the value of the gamma function over the entire real double precision floating-point range. It means that for every double precision floating-point number x except the poles −k for 0 ≤ k ∈ N the true value of Γ(x) is included within an almost maximally accurate interval with floating-point bounds. The application to interv...

Implementation of silicon-quantum-dots (Si-QDs) as a floating gate in metal-oxide-semiconductor field-effect transistors (MOSFETs) has received increasing attention because of its potential advantage for multivalued memories operating reliably even at room temperature and above [1-3]. In this work, we focused on electron storage in Si-QDs stack structures and studied electron charging, discharg...

Calcareous floating periphyton mats in the southern Everglades provide habitat for a diverse macroinvertebrate community that has not been well characterized. Our study described this community in an oligotrophic marsh, compared it with the macroinvertebrate community associated with adjacent epiphytic algae attached to macrophytes in the water column, and detected spatial patterns in density a...

A brief description is provided of the decimal floating-point support available for Intel® Architecture processors, compliant with the IEEE Standard 754-2008 for Floating-Point Arithmetic [1]. Some performance results are included.

The floating-gate transistor can be used to design analog circuits, such as current mirrors [1], current scaler[2] and current multiplier [3, 4] and divider [4]. The multiple input floating-gate transistor can be used to design ultra lowvoltage “pseudo differential” pairs [1], hence ULV rail-to-rail amplifiers and analog multipliers are feasible using the floating-gate technique. In this paper ...

ÐThis paper presents a floating-point addition algorithm and adder pipeline design employing a packet forwarding pipeline paradigm. The packet forwarding format and the proposed algorithms constitute a new paradigm for handling data hazards in deeply pipelined floating-point pipelines. The addition and rounding algorithms employ a four stage execution phase pipeline with each stage suitable for...

Due to recent technological developments, high-performance floating-point signal processing can, for the first time, be easily achieved using FPGAs. To date, virtually all FPGA-based signal processing has been implemented using fixed-point operations. This white paper describes how floating-point technology on FPGAs is not only practical now, but that processing rates of one trillion floating-p...

The "floating" posterior inferior glenohumeral ligament (floating PIGHL) is an uncommon cause of posterior shoulder instability. This pathologic lesion, defined as detachment of both the origin of the PIGHL (posterior Bankart lesion) and insertion of the of the PIGHL from its humeral head insertion site, often results in significant and persistent shoulder instability symptoms. An effective sur...