Multi-core architectures are becoming mainstream, permitting increasing on-chip parallelism through hardware support for multithreading. Synchronization, especial finegrain synchronization, is essential to the effective utilization of the computational power of high-performance large-scale multi-core architectures. However, designing and implementing fine-grain synchronization in such architect...

Present production of rice is far below its reported potential yield because of being Ndeficiency, the major constraint. Because of poverty, small farmers have to rely on native soil N-supply. Between wheat harvest and rice transplanting, a dry-to-wet season transition (DWT) period exist with changing soil moisture from aerobic to anaerobic and a large amount of native soil N loss is hypothesiz...

A safe basis for automatic loop parallelization is the polyhedron model which represents the iteration domain of a loop nest as a polyhedron in Zn. However, turning the parallel loop program in the model to efficient code meets with several obstacles, due to which performance may deteriorate seriously – especially on distributed memory architectures. We introduce a fine-grained model of the com...

A five-stage pipelined CPU based on the MIPs ISA is mapped to a self-timed logic family known as Phased Logic (PL). The mapping is performed automatically from a netlist of D-Flip-Flops and 4-input Lookup Tables (LUT4s) to a netlist of Phased Logic gates. Each PL gate implements a 4-input Lookup Table in addition to control logic required for the PL control scheme. PL offers a speedup technique...

In this research, I explore how distributed applications can achieve fine-grain adaptation in a mobile environment. I put forth the thesis that this can be achieved by exploiting context information, and support the idea with two applications: browsing the web on a mobile device, and continuous remote health monitoring of individuals.

Increase in FPGA capacity combined with CMOS technology scaling has resulted in increased demands on the configurable wiring architecture. Modern FPGAs typically give over 50% of the reconfigurable area over to routing resources. Rent’s Rule [1,2] implies that static FPGA wiring is not scalable and we are approaching the point where cross chip communication is impossible within a clock cycle. I...

Database applications often require rigorous provenance; e.g., it is important to know who is responsible for a change and at what time a change was done. Additionally, it is important to know which program, rule, or model was executed, and which data was used as input. The standard solution is to include provenance into the application logic. The consequence is that such a program extends sign...

We consider how to distribute sparse matrices among processors to reduce communication cost in parallel sparse matrix computations, in particular, sparse matrix-vector multiplication. We allow 2d distributions, where the distribution (partitioning) is not constrained to just rows or columns. The fine-grain model is a 2d distribution introduced in [2] where nonzeros can be assigned to processors...

In this thesis, we apply the pattern recognition and data processing strengths of machine learning to accomplish traffic analysis objectives. Traffic analysis relies on the use of observable features of encrypted traffic in order to infer plaintext contents. We apply a clustering technique to HTTPS encrypted traffic on websites covering medical, legal and financial topics and achieve accuracy r...