DSP Application requires a fast computations & flexibility of the design. Partial Reconfiguration (PR) is an advanced technique, which improves the flexibility of FPGAs by allowing portions of a design to be reconfigured at runtime by overwriting parts of the configuration memory. In this paper we are using microblaze soft core processor & ICAP Port to reconfigure the FPGA at runtime. ICAP is a...

The main focus of the paper is to bring out the differences in performance related issues of Fast-ICA algorithm associated with floating point and fixed point digital signal processing (DSP) platforms. The DSP platforms consisting of TMS320C6713 floating point processor and TMS320C6416 fixed point processor from Texas Instruments have been chosen for this purpose. To study the consistency of pe...

In this paper, a new RF/Microwave source is presented. This source is able to generate a Continuous Waveform (CW) signal as well as a modulated signal like GFSK for Bluetooth and GMSK for GSM. The RF source presented here is based on a direct modulation All-Digital Phase-Locked-Loop (ADPLL) architecture that was originally designed for a Bluetooth transmitter in the 2.4GHz in industry, science,...

A digital signal processor (DSP) solution is proposed to control an H-bridge DC-DC isolated output power converter. The multiple mode digital controller is evaluated with an existing Westinghouse 1-kW power stage. The digital controller was developed using the dSPACE [1] rapid prototype development system and MATLAB/Simulink. It is evaluated using a real-time digital control development platfor...

Software-defined radio (SDR) is an emerging technology that facilitates having multiple wireless communication protocols on one device. Previous work has shown that current W-CDMA, GPS, GSM, and WiMAX applications can run on this class of device while consuming significant processing power. Next generation wireless networks require speeds in excess of 50Mbps. Some of the fastest AES software im...

The Mobile Multimedia Modem (M3)-DSP is based on a scalable, highly parallel DSP platform concept capable of delivering the processing power to create software solutions for tasks that are currently considered ASIC-only domains, e.g. xDSL or IEEE 802.11a. The platform, consisting of the parallel signal processing engine and an Input-/ Output Processor (IOP) is introduced with features which are...

Real-time signal, image, and control applications have very important time constraints, involving the use of several powerful numerical calculation units. The aim of our work is to develop a fast and automatic prototyping process dedicated to parallel architectures made of both PC and several last generation Texas Instruments digital signal processors: TMS320C6X DSP. The process is based on Syn...

This paper presents the architecture of an asynchronous array of simple processors (AsAP), and evaluates its key architectural features as well as its performance and energy efficiency. The AsAP processor calculates DSP applications with high energyefficiency, is capable of high-performance, is easily scalable, and is well-suited to future fabrication technologies. It is composed of a two-dimen...

In this paper a DSP-based active contour model for tracking of the endocardium in a sequence of echocardiographic images is presented. If a contour is available in the first frame of a sequence, the contours in the subsequent frames are segmented. Deformable active contours is a technique that combine geometry, physics and approximation theory in order to solve problems of fundamental importanc...

-The permanent magnet linear synchronous motor (PMLSM) is sensitive to various disturbances such as the load disturbances, parameter perturbations, end effect and so on. To overcome this trouble, a new nonlinear robust controller using the homogeneity-based higher-order sliding mode control technique for the PMLSM is proposed. The detailed systematic controller design procedure is discussed. A ...