نتایج جستجو برای: delay locked loop dll
تعداد نتایج: 269676 فیلتر نتایج به سال:
A highly integrated 40 Gbit/s coherent optical receiver is reported using a Costas loop as a homodyne optical phase locked loop (OPLL). A photonic IC, an electrical IC, and a hybrid loop filter are characterized, and the feedback loop system is fully analyzed to build a stable homodyne OPLL. All components are integrated on a single substrate within the compact size of 10 × 10mm(2), and a 1.1 G...
From the perspective of differential phase delay experienced by two counterpropagating optical fields, self-starting mode-locked fiber laser with a non-linear amplifying loop mirror (NALM) is theoretically studied. Although it generally believed that NALM shows saturable absorption effect on both continuous wave (CW) light and pulses, we find counter-intuitive fact cross-phase modulation (XPM) ...
1. Definition. A PLL is a feedback system that includes a VCO, phase detector, and low pass filter within its loop. Its purpose is to force the VCO to replicate and track the frequency and phase at the input when in lock. The PLL is a control system allowing one oscillator to track with another. It is possible to have a phase offset between input and output, but when locked, the frequencies mus...
This paper presents a wide range fast lock all-digital deskew buffer using a digital controlled delay line, which achieves low jitter, fast lock, low power consumption and 50% duty cycle correction. A cyclic time-to-digital converter is introduced to decrease the locking time in conventional register-controlled delay-locked loop. A balanced edge combiner to achieve 50% output clock is also pres...
In this paper the choice of DLL parameters is studied with special focus on multipath and Doppler sensitivity. The envisaged application is code tracking on navigation receivers and the multipath fading environments defined for next generation navigation systems are considered. Given the particular properties of these propagation environments, multipath estimating delay lock loop is shown to ha...
طراحی PLL دو حلقه ای مبتنی بر آشکارسازی فاز پنجرهای با سرعت قفل بالا، توان مصرفی و اسپور مرجع پایین
In this paper, a dual loop PLL with short locking time, low power consumption and low reference spur is presented. The output frequency and reference frequency of the designed circuit are 3.2 GHz and 50 MHz, respectively, aimed to WiMAX applications. In the proposed circuit in locked state, some parts of the circuit could be powered off, to reduce overall power consumption. Phase detection in t...
With the development of designing and manufacturing level for micro-electromechanical system (MEMS) gyroscopes, control circuit has become a key point to determine their internal performance. Nevertheless, phase delay electronic components may result in some serious hazards. This study described real-time correction MEMS vibratory gyroscopes. A detailed theoretical analysis was provided clarify...
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