In this paper, we propose a gate-level NBTI delay degradation model, where the stress voltage variability due to PMOS transistors’ stacking effect is considered for the first time. Experimental results show that our gate-level NBTI delay degradation model results in a tighten upper bound for circuit performance analysis. The traditional circuit degradation analysis leads to on average 59.3% ove...

A transistor sizing algorithm for row-based layouts is presented under a improved area model. This algorithm uses convex programming to nd a minimal area circuit for a given delay speci cation. The new area model uses a concept of row heights as opposed to the conventional metric of sum of gate sizes. Results over a number of circuit indicate a signi cant reduction both in the minimum delay ach...

An overview of performance analysis and comparison between various parameters of a low power high speed 10T full adder has been presented here. This paper shows comparative study of advancement over active power, leakage current and delay with power supply of (0.7v) .We have achieved reduction in active power consumption of 39.20 nW and propagation delay of 10.51 ns, which makes this circuit hi...

In this paper, an analytical delay model of Source-Coupled Logic (SCL) gates is proposed. In particular, the multiplexer, the XOR and the D-latch gates are considered. The method starts from a linearization of SCL gates, and analysis of the equivalent circuit obtained is simplified by introducing the dominant-pole approximation. The delay expression obtained is quite simple and each term has an...

Early circuit performance estimation and easy-to-apply methods for minimum-delay gate sizing are needed, in order to enhance circuit’s performance and to increase designers’ productivity. In this paper, we present a practical method to perform gate sizing, taking also into account the contribution of fixed wiring loads. Closed-form bounds are derived and a simple recursive procedure is develope...

This paper presents a novel approach for identifying non-robustly unsensitizable paths using the bounded gate delay model. It is shown that many non-robust paths will remain undetected unless the delay values are calculated at the path level rather than considering calculations at the circuit level bounded delay. As an initial step a canonical data structure is generated where each circuit path...

This paper addresses low-power circuit design for delay-constrained portions of cutting-edge ICs, in which scaled threshold voltages have made leakage power consumption a major concern. Assuming parameters for a dual-VT 0.10-μm process generation, we analyze two different circuits, using low-VT and high-VT devices, respectively, obeying an identical delay constraint. The power consumption compa...

In this paper, we propose a novel technique for post-layout delay optimization. This technique identi es the Boolean space corresponding to late arriving transitions at the outputs of delay-critical subcircuits within the given circuit. There transitions are eliminated from the outputs by implementing the corresponding logic separately and merging them with the original circuit through some con...

The Stop-and-Go service discipline allows a rate-controlled Virtual Circuit to obtain (small) delay-jitter bounds independent of the number of hops along its path. This may prove to be desirable for isochronous applications in wide-area virtual circuit networks. We consider how to integrate the Stop-and-Go and Hierarchical Round Robin service disciplines to allow delay-jitter bounded communicat...

Implementation of delay-insensitive (DI) or unordered codes is the subject of this report. We present two diierent architectures for decoding systematic DI codes: (a) enumeration-based decoder, and (b) comparison-based decoder. We argue that enumeration-based decoders are often impractical for many realistic codes. Comparison-based decoders that detect arrival of a code word by comparing the re...