An unsigned 8-bit ÷ 4-bit delay-insensitive iterative divider is developed using the NULL Convention Logic paradigm. The divider is simulated using a 0.5μm CMOS process with static cells. The simulation of the initial design yielded an average cycle time of 75.92 ns with a transistor count of 4,721. A subsequent design increased throughput by 18%, while only increasing area by 2.7%.

The traceability chain to derive the capacitance unit from the quantum Hall resistance coaxial bridges. These bridges employ a inductive voltage divider to provide the voltage ratio needed. One such divider has recently been constructed calibrated at Inmetro. The design techniques responsible for the small ratio errors of the device are detailed

A realization of the CMOS digitally programmable current follower (DP-CF) suitable for low-voltage high-frequency application is presented. To achieve very low input resistance, it is realized using a modification of a low-input resistance stage as an input stage. To achieve the precise digital control of the current gain, the current division technique is used. The proposed DP-CF can operate w...

A gas permeation model (Coupling Model) has been developed which has the flexibility to be used for different membrane module configurations. The aim of this work is to predict the performance of a single stage gas separation process using membranes and provide a comprehensive description of process parameters like flow rates, composition, stage cut and stream pressure. The significant feature ...

We realize and investigate a wavelength-flexible phase-coherent all-optical frequency-by-2 divider. Frequency division is obtained via self-phase locking in a degenerate continuous-wave (cw) optical parametric oscillator (OPO). The wavelength flexibility of the divider is based on the use of quasiphase matching (QPM) with perpendicular polarizations of the OPO output waves (type II). Mutual inj...

An 8-bit programmable square finder cum frequency divider architecture is presented. This special architecture includes a high speed parallel counter, clock trigger circuit, eight bit multiplier logic, sequence termination logic and sequence restarter logic. The entire architecture is divided into two parts: The frequency divider section and the square finder section. The frequency divider circ...

The Karlsruhe Tritium Neutrino Experiment (KATRIN) aims to determine the absolute mass of the electron antineutrino from a precise measurement of the tritium β-spectrum near its endpoint at 18.6 keV with a sensitivity of 0.2 eV/c. KATRIN uses an electrostatic retardation spectrometer of MAC-E filter type for which it is crucial to monitor high voltages of up to 35 kV with a precision and long-t...