Unfortunately there are some problems in deIn this paper, we present a n e f i c i e n t and accurate’ IDDQ faul t modeling technique f o r digital CMOS circuit. Both, the normal and faul ty “current” behaviors of a CMOS digital circuit can be described by th i s model. Also the parasit ic capacitive and induct ive parameters can be emulaled. A f o r m a l method f o r creating this model f r o...

Characteristics of various CMOS and NMOS circuit techniques are described, along with the shortcomings of each. Then a new circuit ty#e, the CMOS domino circuit, will be described. This involves tbe connection of dynamic CMOS gates in such a way that a single clock edge can be used to turn on all gates in the circuit at once. As a result, complex clocking schemes are not needed and the full inh...

Conceptual memristors have recently gathered wider interest due to their diverse application in non-von Neumann computing, machine learning, neuromorphic computing, and chaotic circuits. We introduce a compact CMOS circuit that emulates idealized memristor characteristics and can bridge the gap between concepts to chip-scale realization by transcending device challenges. The CMOS memristor circ...

Three test circuits have been developed to experimentally demonstrate and stress the state-of-the-art in 3D integrated systems. Several critical elements of this emerging technology, synchronization, power delivery, and thermal management, are just beginning to be explored. The three test circuits explore these three fundamental design issues. The first test circuit examines multi-plane synchro...

Abstmet-A novel way of implementing the Leading Zero Detector (LZD) circuit is pmsented. The implementation is b a d on an algorithmic approach resulting in a modular and scalable circuit for any number of bits. We designed a 32 and 64 bit leading zero detector circuit in CMOS and ECL technology. The CMOS version was designed using both logic synthesis and an algorithmic approach. The algorithm...

This paper presents a low-voltage, low-power and faulttolerant implementation of Double Sideband Suppressed Carrier (DSB-SC) amplitude modulator-demodulator circuit for portable communication systems. Through the approximation proposed in this work, a CMOS four quadrant multiplier is used as a (de)modulator circuit to generate DSB-SC (de)modulated signals. Furthermore, the proposed fault-tolera...