In this paper, an approach is proposed for extracting coupled RLC network from multi-level interconnects. The proposed approach starts with a step of partitioning the layout of the full-chip under consideration into several sublayouts, followed by steps of fracturing the partitioned layout and transforming into the three-dimensional structure. The layout is then classified into three species of...

To reduce manufacturing variation due to chemicalmechanical polishing and to improve yield, layout must be made uniform with respect to density criteria. This is achieved by layout postprocessing to add ll geometries, either at the foundry or, for better convergence of performance veri cation ows, during layout synthesis [10]. This paper proposes a new min-variation objective for the synthesis ...

To mitigate the radio-frequency (RF) performance degradation caused by electrostatic discharge (ESD) protection device, low capacitance (low-C) design on ESD protection device is a solution. With the smaller layout area and small parasitic capacitance under the same ESD robustness, silicon-controlled rectifier (SCR) device has been used as an effective on-chip ESD protection device in RF ICs. I...

This paper presents a framework for verifying compilation tools for parametrised hardware libraries with placement information. Such libraries are captured in Pebble, a simple declarative language based on Structural VHDL, and can contain placement information to guide circuit layout. Relative placement information enables control of circuit layout at a higher level of abstraction than placemen...

This paper presents a freeware EDA framework for teaching mixed-mode full-custom VLSI design. The proposed set of EDA tools and associated physical design kit (PDK) allows students to gain handson experience on ASIC design tasks covering schematic entry, both at system and circuit levels, HDL system simulation and block specification, automatic circuit optimization, PCell-based layout, physical...

high output power density VHF converter has become important in recent years. This output power density of the converter is experiencing an adverse effect resulted from the applied switching frequency. In addition, the frequency which is higher than 20 MHz will no longer be applicable on the discreet SMT technology hence lowers the output power density. Thus, further improvement on circuit anal...

In general, automatic layout composition techniques based on pre-designed devices facilitate the production of small IC numbers by prefabricating their basic structures. They also enables a high degree of automatic layout synthesis. However, for their correct electrical behavior it is essential, that potential problems caused by electro-magnetic compatibility (EMC) are fully considered during t...

The bigraph crossing problem, embedding the two vertex sets of a bipartite graph G = (V0; V1; E) along two parallel lines so that edge crossings are minimized, has application to circuit layout and graph drawing. We consider the case where both V0 and V1 can be permuted arbitrarily | both this and the case where the order of one vertex set is xed are NP-hard. Two new heuristics that perform wel...

End of the roadmap integrated circuit interconnects suffer from capacitance variability due to line edge roughness (LER), significantly impacting overall circuit performance. We forecast the capacitance variability of short range interconnects with realistic line edge roughness at the upcoming 45, 32, and 22 nm technology nodes using a fast TCAD capacitance tool. Capacitance variability is layo...

Process variations are a major bottleneck for digital CMOS integrated circuits manufacturability and yield. That is why regular techniques with different degrees of regularity are emerging as possible solutions. Our proposal is a new regular layout design technique called Via-Configurable Transistors Array (VCTA) that pushes to the limit circuit layout regularity for devices and interconnects i...