We consider the problem of computing the Hamming weight of an n-bit vector using a circuit with gates for addition and multiplication modulo 2 (alternatively, XOR and conjunction gates) only. The number of multiplications necessary and sufficient to build such a circuit is called the “multiplicative complexity” of the Hamming weight function, and is denoted by c∧(H). We prove c∧(H) = n−HN(n) wh...

Today, one of the biggest problems that gripped the banking sphere, the high cost of implementing advanced technologies and the efficient use of the hardware. Cloud computing is the use of shared services on the Internet provides a large role in developing the banking system, without the need for operating expenses including staffing, equipment, hardware and software Reducing the cost of implem...

Restoring and non-restoring divider has become widely applicability in the era of digital computing application due to its computation speed. In this paper, we have proposed the design of divider of different architecture for the computation of Vedic sutra based. The design of divider in the Vedic mode results in high computation throughput due to its replica architecture, where latency is mini...

The approaching end of traditional MOSFET technology scaling creates the need to identify novel devices, manufacturing technologies, memories, and architectures to preserve digital computing performance scaling. To this end, we argue for the need to generate circuit-level models and integrate them into existing simulation and digital design infrastructure for rapid architectural design explorat...

in this paper, the electrochemical behaviour of passive films formed on aisi 321 stainless steel (aisi 321)immersed in 0.1 m naoh + 0.1 m koh solution was evaluated by different electrochemical techniques. forthis purpose, passive films were formed at open circuit potential for 1 to 12 hours and then electrochemicalmeasurements were done. the polarization curves suggested that aisi 321 showed e...

This paper presents an improved measure for the dynamic functionality of a logic circuit, called delay fault probability (DFP). The new measure reflects both the nominal delay of the paths and the fact that only few paths are critical for path delay fault testing. An efficient distributed algorithm for computing DFP is presented. The experimental results show that, in contrast to DFP, the conve...

Optical transimpedance receivers implemented in CMOS VLSI technologies are modeled and optimized for freespace optoelectronic interconnections. Sensitivity, bandwidth, power dissipation, and circuit area are analyzed for receivers using three different submicron CMOS processes. A comparison with the circuit noise limited optical power indicates that, for digital computing applications, the rece...

In this paper, a low-complexity current-mode Winner-Take-All circuit (WTA) of O(n) complexity with logical outputs is presented. The proposed approach employs a Quasi-FG Inverter as the key element for current integration and the computing of the winning cell. The design was implemented in a double-poly, three metal layers, 0.5m CMOS technology. The circuit exhibits a good accuracy-speed trade...

This paper presents a method of learning to solve design problems by generalizing examples. The technique has been developed in the domain of logic circuit design. It involves the use of domain knowledge to analyze examples and produce generalized circuit designs. The method utilizes proofs of design correctness to guide the process of generalization. Our approach is illustrated by showing it c...

in order to improve the level of intelligence, availability, being on demand, convenience, information and humanization of rural public transportation systems, they are more willing to use modern information and communicative technologies. in addition to management services, intelligent transportation systems can provide passengers, drivers, travel agencies and other institutions with other ser...