In this article we present a structured approach to formal hardware verification bymodeling circuits at the register-transfer level using a restricted form of higher-order logic. Thisrestricted form of higher-order logic is sufficient for obtaining succinct descriptions of hierarchicallydesigned register-transfer circuits. By exploiting the structure of the underlying hardware proof...

Timing analysis plays a vital role in chip design, which analyze whether a chip design meets the timing constraints. The main objectives of timing analysis are speed and accuracy. There are two engines for timing analysis namely Statistical Timing Analysis (STA) and Statistical Static Timing Analysis (SSTA). VLSI CAD has been gaining a lot of interest in both STA and SSTA. As technology continu...

In many application domains in VLSI CAD, like formal verification or test pattern generation, the problem to be solved can be formulated as an instance of satisfiability (SAT). The SAT instance in this cases is usually derived from a circuit description. In this paper we propose to use techniques known from logic synthesis to speed up SAT solvers. By experiments it is shown that these technique...

In this paper we investigate the design of macro-cell generators of division and square root floating-point operators. The number representation used in our operators is the IEEE-754-1985 standard for binary floating-point numbers. The design and implementation of the generators rely on a powerful multiview layout synthesis tool called GenOptim. This CAD tool is able to output a set of differen...

With the rapid developments in very large-scale integration (VLSI) technology, design and computer-aided design (CAD) techniques, at both the chip and package level, the operating frequencies are fast reaching the vicinity of gigahertz and switching times are getting to the subnanosecond levels. The ever increasing quest for high-speed applications is placing higher demands on interconnect perf...

Minimum spanning tree problem is a very important problem in VLSI CAD. Given n points in a plane, a minimum spanning tree is a set of edges which connects all the points and has a minimum total length. A naive approach enumerates edges on all pairs of points and takes at least (n 2) time. More eecient approaches nd a minimum spanning tree only among edges in the Delaunay triangulation of the po...

Dynamic domino logic circuits are widely used in modern digital VLSI circuits. These dynamic circuits are often favored in high performance designs because of the speed advantage offered over static CMOS logic circuits. The main drawbacks of dynamic logic are lack of design automation and less tolerance to noise. In performance-critical applications, Domino logic is widely employed since it has...

Decision Diagrams (DDs) are a data structure for the representation and manipulation of discrete logic functions often applied in VLSI CAD. Common DDs to represent Boolean functions are Binary Decision Diagrams (BDDs). Multiple-valued logic functions can be represented by Multiple-valued Decision Diagrams (MDDs). The efficiency of a DD representation strongly depends on the variable ordering; t...

Binary decision diagrams (BDD) have gained a wide acceptance as a mathematical model for representation and manipulation of Boolean functions in VLSI CAD. In this paper we consider a special kind of BDDs called Structurally Synthesized BDDs (SSBDDs), which have an important characteristic property of keeping information about circuit’s structure. Despite the fact that the SSBDD model itself is ...

Gate-arrays are the most common design style for semicus-tom VLSI integrated circuits. An important part of the gate-array design process is the routing of wires between the logic elements, which is an extremely compute-intensive operation. This paper presents an algorithm for routing gate-arrays that uses a hypercube connected parallel processor to provide the necessary computation power. In o...