The dynamics of a delayed mathematical model for Hes1 oscillatory expression are investigated. The linear stability of positive equilibrium and existence of local Hopf bifurcation are studied. Moreover, the global existence of large periodic solutions has been established due to the global bifurcation theorem. Keywords—Hes1, Hopf bifurcation, time delay, transcriptional repression loop

In this paper, a delayed Nicholson,s blowflies model with a linear harvesting term is investigated. Regarding the delay as a bifurcation parameter, we show that Hopf bifurcation will occur when the delay crosses a critical value. Numerical simulations supporting the theoretical findings are carried out. Keywords—Nicholson,s blowflies model; Stability; Hopf bifurcation; Delay.

In this paper, a delayed predator–prey system with stage structure is investigated. Sufficient conditions for the system to have multiple periodic solutions are obtained when the delay is sufficiently large by applying Bendixson’s criterion. Further, some numerical examples are given. Keywords—Predator-prey system, Stage structure, Hopf bifurcation, Periodic solutions.

A first-order delayed chaotic model with n-double scroll attractors is investigated. The associated piecewise-linear activation function requires only a few operational amplifiers, which can easily be realized by an electronic circuit. The typical waveforms and phase portraits are plotted to illustrate n-double scroll chaotic oscillations. Keywords—delay; chaotic attractor; n-double scroll; cir...

A robust algorithm is developed for jointly controlling the power and rate of flow in a distributed wireless network. The dynamics of the network is modelled as a discrete-time state-delayed system with uncertainties and the proposed algorithm achieves better SIR performance than a conventional power control scheme. keywords: Robust estimation, congestion control, power control, rate control, w...

We present a technique, termed clockgenerating (CG) domino, for improving dual-output domino logic that reduces area, clock load, and power without increasing the delay. A delayed clock, generated from certain dual-output gates, is used to convert other dual-output gates to single output. Simulation results with ISCAS 85 benchmark circuits indicate an average reduction in area, clock load, and ...