Testing of present day VLSI circuits with standard linear scan procedures using the Built-In Self Test (BIST) takes a significant amount of time, with the sheer number of sequential elements running into tens of thousands. Using the Illinois Scan Architecture, we propose to significantly reduce the test application time, by dividing the scan chain into multiple partitions and shifting in the sa...

This paper proposes a new BIST (Built-In Self-Test) method for static testing of an ADC (Analog-to-Digital Converter) with transition detection method. The proposed BIST uses a triangle-wave as an input test stimulus and calculates the ADC’s static parameters. Simulation results show that the proposed BIST can test both rising and falling transitions with minimal hardware overhead. key words: A...

In this paper, we present our multilingual dependency parser developed for the CoNLL 2017 UD Shared Task dealing with “Multilingual Parsing from Raw Text to Universal Dependencies”1. Our parser extends the monolingual BIST-parser as a multi-source multilingual trainable parser. Thanks to multilingual word embeddings and one hot encodings for languages, our system can use both monolingual and mu...

This paper presents a discussion on several methods that can be used to improve the testability of mixed-signal integrated circuits. We begin by outlining the role of test, and its impact on product cost and quality. A brief look at the pending test crises for mixedsignal circuits is also considered. Subsequently, we shall outline several common test strategies, and their corresponding test set...

In this paper, we propose a new transparent built-in self-test ( TBIST ) method to test multiple embedded memory arrays with various sizes in parallel. First, a new transparent test interface is designed to perform testing in the normal mode and to cope with nested interrupts in a realtime manner. The circular scan test interface facilitates the processes of both test pattern generation and sig...

This paper presents the implementation and results of the test suite for DSM ASIC consisting of static, ∆Iddq, and dynamic patterns based on scan, and quantitatively reports the advantages of dynamic pattern over AC static pattern, even at a low frequency, and advantages of ∆Iddq test over traditional Iddq. A defect level calculation method is presented which decomposes the defect level into, a...

Existing high-level BIST synthesis methods focus on one objective, minimizing either area overhead or test time. Hence, those methods do not render exploration of large design space, which may result in a local optimum. In this paper, we present a method which aims to address the problem. Our method tries to find an optimal register assignment for each k-test session. Therefore, it offers a ran...

Testing of high performance integrated circuits is becoming increasingly a challenging task owing to high clock frequencies. Often testers are not able to test such devices due to their limited high frequency capabilities. In this article we outline a Design-for-Test methodology such that high performance devices can be tested on relatively low performance testers. In addition, a BIST framework...

We introduce a two-staged Genetic Algorithm for optimizing weighted random pattern testing in a Built-InSelf-Test (BIST) environment. The first stage includes the OBDD-based optimization of input probabilities with regard to the expected test length. The optimization itself is constrained to discrete weight values which can directly be integrated in a BIST environment. During the second stage, ...

This paper presents an attempt towards design quality improvement by incorporating of self-testability features during dada path (high-level) synthesis. This method is based on the use of test resource sharing possibilities to improve the self-testability of the circuit. This is achieved by incorporating testability constraints during register assignment. Experimental results are presented to d...