When stuck-at faults are targeted, scan design reduces the complexity of the test problem. But for delay fault testing, the standard scan structures are not so efficient, because delay fault testing requires the application of dedicated consecutive two-pattern tests. In a standard scan environment, pre-determined two pattern tests cannot be applied to the circuit under test because of the seria...

In this paper we present a novel method for reliability testing of MEMS devices containing movable structures. A small size, simple and cheap vibration fatigue test equipment was designed and realized at BUTE and vibration fatigue tests were carried out on 10 samples of a LIS0L02AS4-type MEMS 3-axis inertial sensor provided by ST Microelectronics. The paper presents the test plan, the test equi...

.............................................................................................................................. ii Acknowledgements ............................................................................................................ iii List of Figures .................................................................................................................... vi L...

In this paper, we present a BIST technique that measures the RMS value of a Gaussian distribution period jitter. In the proposed approach, the signal under test is delayed by two different delay values and the probabilities it leads the two delayed signals are measured. The RMS jitter can then be derived from the probabilities and the delay values. Behavior and circuit simulations are performed...

Built-In Self-Test (BIST) techniques constitute an attractive and practical solution to the problem of testing VLSI circuits and systems. Input vector monitoring concurrent BIST schemes perform testing concurrently with the operation of the circuit. In this paper a novel input vector monitoring concurrent BIST scheme is presented that compares favorably to previously proposed schemes with respe...

The design and architecture of a memory test synthesis framework for automatic generation, insertion and veriication of memory BIST units is presented. We use a building block architecture which results in full customization of memory BIST units. The exibility and eeciency of the framework are demonstrated by showing that memory BIST units with diierent architecture and characteristics could be...

1 This work was supported by DFG grant WU 245/1-3 Abstract Power consumption of digital systems may increase significantly during testing. In this paper, systems equipped with a scan-based built-in self-test like the STUMPS architecture are analyzed, the modules and modes with the highest power consumption are identified, and design modifications to reduce power consumption are proposed. The de...

This paper concerns design and realization of programmable emulator of mechanical loads for motors. The aim of this paper is to build integrated test equipment, which will allow realistic testing of drive parameters and mainly quality of control structures on controlling different kinds of loads. For this purpose create user-friendly software which will allow emulation of physical system in rea...

In this paper, we present a new low power scan-based BIST technique which can reduce the switching activity during test operation. The proposed low power /energy technique is based on a gated clock scheme for the scan path and the clock tree feeding the scan path.