This paper presents flit-reservation flow control, in which control flits traverse the network in advance of data flits, reserving buffers and channel bandwidth. Flit-reservation flow control requires control flits to precede data flits, which can be realized through fast on-chip control wires or the pipelining of control flits one or more cycles ahead of data flits. Scheduling ahead of data ar...

Asymmetric forms of acetylcholinesterase (AChE) are thought to be the predominant forms of this enzyme at vertebrate neuromuscular junctions where they attach to the synaptic basal lamina via a collagen-like tail. High salt and heparin-containing buffers are capable of solubilizing asymmetric AChE molecules from skeletal muscle; however, detachment of AChE specifically from synaptic basal lamin...

We studied the effects of periodic disturbance (prescribed burning and light disking) and landscape composition on nest density and success for grassland birds in agricultural conservation buffers in southeastern United States agroecosystems. During the 2007–2009 breeding seasons, we located 387 nests in buffers of a northeast Mississippi agroecosystem. Dickcissel (Spiza americana) and red-wing...

Today all Internet routers are built with buffers that hold packets in times of congestion. These buffers can typically store between 250ms to one second worth of data. According to a widely used “rule-of-thumb”, a link needs a buffer of size B = RTT × C, where RTT is the average round-trip time of a flow passing across the link, and C is the data rate of the link. For example, a 10Gb/s router ...

Wire latency across the links of a NoC potentially limit available bandwidth, especially in deep submicron technology. Pipeline buffers may be placed on long links to increase throughput and flit buffering. In asynchronous (clockless) NoCs, this can be done to only those links that will yield benefits, and is especially useful in heterogeneous embedded SoCs with irregular layouts and traffic. W...

Contention resolution and forwarding of labeled optical packets at 40 Gb/s is demonstrated utilizing multiple InP based optical buffers and monolithic wavelength converters. Layer-2 packet recovery measurements are presented. ©2009 Optical Society of America OCIS codes: (060.1810) Buffers, couplers, routers, switches, and multiplexers; (060.6719) Switching, packet

A technique for workload balancing on distributed visualization clusters is suggested. The round-robin scheduling of partial object geometry “chunks” avoids render node starvation and balances the data backlog in the send buffers of the geometry nodes. Because frame synchronization requires that all send buffers drain, balancing these send buffer backlogs is seen to substantially improve frame ...

All packet switches contain packet buffers to hold packets during times of congestion. The capacity of a high performance router is often dictated by the speed of its packet buffers. This is particularly true for a shared memory switch where the memory needs to operate at times the line rate, where is the number of ports in the system. Even input queued switches must be able to buffer packets a...

Contemporary graphics architectures are based on a hardware-:-supported geometric pipeline, a rasterizer, a z-buffer and two frame buffers. Additional pixel memory is used for alpha blending and for storing logical information. Although their functionality is growing it is still limited because of the fixed use of pixel memory and the restricted set of operations provided by these architectures...