Changes in control ow, caused primarily by conditional branches, are a prime impediment to the performance of wide-issue superscalar processors. This paper investigates a block-level prediction scheme to mitigate the e ects of control ow changes caused by conditional branches. Instead of predicting the outcome of each conditional branch individually, this scheme predicts the target of a sequent...

As contemporary microprocessor design attempt to expose additional instruction level parallelism (ILP), data value speculation has become a mainstream microarchitectural feature. Many different value speculation techniques have been proposed. The goals are to both achieve a high prediction rate, while predicting values for critical instructions. One key issue is how value-based speculation affe...

Recent superscalar processors that use deep pipelines and wide issue rates, highly depend on eecient branch prediction to obtain a large amount of instruction-level parallelism. Much work has been carried out in this area and the outcome of branches is very predictable. Mostly, su-perscalar processors are used in a multiprogram-ming environment to obtain higher throughput. In this paper, we ana...

As contemporary microprocessor design attempt to expose additional instruction level parallelism (ILP), data value speculation has become a mainstream microarchitectural feature. Many different value speculation techniques have been proposed. The goals are to both achieve a high prediction rate, while predicting values for critical instructions. One key issue is how value-based speculation affe...