The present study evaluates four designs of XOR using our previously reported two-phase clocked adiabatic static CMOS logic (2PASCL) circuit techniques. 2PASCL XOR, which demonstrates the lowest power dissipation, is used for a 4ˆ4-bit array 2PASCL multiplier. Based on simulation results obtained using 0.18 —m standard CMOS technology, at transition frequencies of 1 to 100 MHz, the 4ˆ4-bit arra...

The two-bit multiplier is a simple electronic circuit, small enough to be feasible for evolutionary design, and practically useful as a fundamental building block used in the synthesis of many digital systems. To attain understanding of the evolvability of this digital circuit, we consider its evolutionary design as a search on a fitness landscape. We study the structure of two-bit multiplier l...

This paper proposes design techniques for the efficient VLSI implementation of bit-serial multiplication over a modulus. These techniques reduce multiplication into simple cyclic shifts, where the number representation of the data is chosen appropriately. This representation will, in general, be highly redundant, implying a relatively poor throughput for the multiplier. It is then shown how, by...

In a signal processing like application, the performance of the whole processing is a function of how fast the FFT operation is done .The speed of the operation is directly dependent on efficiency of the multiplier in the design. The paper discusses about a multiplier implementation where the speed of computation is improved by using twin-precision scheme and row decomposition schemes. To lower...

This paper reports on the veriication of two of the IFIP WG10.5 benchmarks | the multi-plier and systolic matrix multiplier. The circuit implementations are timed, detailed gate-level descriptions, and the speciication is given using the temporal logic TL n , a quaternary-valued temporal logic. A practical, integrated theorem-proving/model checking system based on the compositional theory for T...