This paper proposes a micro-code based Programmable Memory BIST (PMBIST) architecture that can support various kinds of test algorithms. The proposed Non-linear PMBIST (NPMBIST) guarantees high flexibility and high fault coverage using not onlyMarch algorithms but also non-linear algorithms such as Walking and Galloping. This NPMBIST has an optimized hardware overhead, since algorithms can be i...

In this paper a new scheme for deterministic and mixed mode scan-based BIST is presented. It relies on a new type of test pattern generator which resembles a programmable Johnson counter and is called folding counter. Both the theoretical background and practical algorithms are presented to characterize a set of deterministic test cubes by a reasonably small number of seeds for a folding counte...

Testing of VLSI chips is changing into significantly complicated day by day as a result of increasing exponential advancement of NANO technology. BIST may be a style technique that enables a system to check mechanically itself with slightly larger system size. During this paper, the simulation result performance achieved by BIST enabled UART design through VHDL programming is enough to compensa...

Register Transfer Level Vladimir Vorisek Institute of Informatics, Slovak Academy of Sciences [email protected] Abstract The poster presents Ph.D. thesis in the area of Test Pattern Generators (TPGs) for application in distributed and embedded Built-In Self-Test (BIST). The goal of this work is to develop a general scheme of designing built-in TPGs for basic arithmetic elements such as adders...

As the compactness of system-on-chip (SoC) increase, it becomes striking to integrate dedicated test logic on a chip. Starting with a broad idea of test problems, this survey paper focus on “Chip” Built in Self-Test (BIST) study and its promotion for board and system-level applications. This paper gives brief informative review of Built-in Self-test (BIST) and its testing techniques. Recently B...

Reliability and robustness have been always important parameters of integrated systems. However, with the emergence of nanotechnologies reliability concerns are arising with an alarming pace. The consequence is an increasing demand of techniques that improve yield as well as lifetime reliability of today’s complex integrated systems. It is requested though, that the solutions result in only min...

This work presents a technique for the generation of analog sinusoidal signals with high spectral quality and reduced circuitry resources. Two integrated demonstrators are presented to show the feasibility of the approach. The proposed generation technique is based on a modified analog filter that provides a sinusoidal output as the response to a DC input. It has the attributes of digital progr...

This paper describes three new march tests for multiport memories. A read (or write) port in such a memory consists of an n-bit address register, an n-to-2n-bit decoder (with column multiplexers for the column addresses) and drivers, and a K -bit data register. This approach gives comprehensive fault coverage for both array and multiport decoder coupling faults. It lends itself to a useful BIST...

This paper describes an approach to hierarchical self tests by use of a test controller. As design for testability and Built-In Self Tests (BIST) at the board level are becoming increasingly important, research has been carried out on formulating test controllers to control test activities. In our approach, instead of providing a fixed test controller design, an automatic synthesis tool is deve...

We propose an autonomous, deterministic scan-BIST architecture that allows compact, precomputed test sets with complete fault coverage to be used for field testing. The use of such short test sequences is desirable in safety-critical systems since it reduces the error latency. It also reduces testing time and therefore allows periodic field testing to be carried out with low system downtime. We...