نتایج جستجو برای: active high decoder

تعداد نتایج: 2416736  

Journal: :EURASIP J. Adv. Sig. Proc. 2010
Olivier Muller Amer Baghdadi Michel Jézéquel

Parallel turbo decoding is becoming mandatory in order to achieve high throughput and to reduce latency, both crucial in emerging digital communication applications. This paper explores and analyzes parallelism techniques in convolutional turbo decoding with the BCJR algorithm. A three-level structured classification of parallelism techniques is proposed and discussed: BCJR metric level paralle...

Journal: :Periodica Polytechnica Electrical Engineering and Computer Science 2019

Journal: :IEEE Transactions on Circuits and Systems for Video Technology 2015

Journal: :SIAM J. Discrete Math. 2011
Shrinivas Kudekar Nicolas Macris

The subject of this paper is transmission over a general class of binary-input memoryless symmetric channels using error correcting codes based on sparse graphs, namely low-density generator-matrix and low-density parity-check codes. The optimal (or ideal) decoder based on the posterior measure over the code bits, and its relationship to the sub-optimal belief propagation decoder, are investiga...

Journal: :International Journal of Computer Science, Engineering and Applications 2012

2010
Gan Ouyang Jun Yan Ren Junyan Ren Lirong Zheng Shili Zhang Hannu Tenhunen Axel Jantsch Ahmed Hemani C. M. Zetterling Mats Brorsson Mohammed Ismail Shaofang Gong Xuejing Wang Liang Liu Jingfeng Li Zhuo Xu Xiaojing Ma Zhigui Liu Cheng Zhang Jun Zhou Wenyan Su Xu Shen Chenxi Li Wei Liang Kai Li Yu Nie

Acknowledgements My deepest gratitude goes first and foremost to Professor Junyan Ren, my supervisor, for his constant encouragement, suggestion and guidance. Second, I would like to express my heartfelt thankfulness to Dr. Fan Ye, who led me into this exciting research area and helped me a lot in the past three years. and Shaofang Gong for traveling thousands of miles from Sweden to Shanghai t...

2016
Ahmed Samy Mohamed Hatem M. Zakaria

This paper presents a pipelined Adaptive Viterbi algorithm of rate 1⁄2 convolutional coding with a constraint length K = 3 which is designed in a reconfigurable hardware to take full advantage of algorithm parallelism, specialization and the throughput rate. In present work, the hardware implementation of the pipelined Adaptive Viterbi algorithm is performed using FPGA processor (Spartan-3AN st...

2012
Tejaswini G. Panse

In this paper, we propose an efficient architecture based on pre-computation for Viterbi decoders incorporating Talgorithm. Through optimization at both algorithm level and architecture level, the new architecture greatly shortens the long critical path introduced by the conventional T-algorithm. The design example provided in this work demonstrates more than twice improvement in clock speed wi...

2016
Claude Berrou Alain Glavieux

Turbo codes are one of the most efficient error correcting code which approaches the Shannon limit. However the major drawback of turbo codes is its high latency due to its iterative decoding process. The high throughput in turbo decoder can be achieved by parallelizing several Soft Input Soft Output(SISO) units together. In this way, multiple SISO decoders work

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