Variables in programs are usually confined to a fixed number of bits and results that require more bits are truncated. Due to the use of 32-bit and 64-bit variables, inadvertent overflows are rare. However, a sound static analysis must reason about overflowing calculations and conversions between unsigned and signed integers; the latter remaining a common source of subtle programming errors. Ra...

Hyper-heuristics can be identified as methodologies that search the space generated by a finite set of low level heuristics for solving search problems. An iterative hyper-heuristic framework can be thought of as requiring a single candidate solution and multiple perturbation low level heuristics. An initially generated complete solution goes through two successive processes (heuristic selectio...

This paper presents a 372ps 64-bit adder using Fast Pull-up Logic (FPL) in 0.18 μm CMOS technology. Fast Pullup Logic is devised and applied to decrease pull-up time which is critical in domino-static adder. The implemented adder measures the worst case delay of 372ps. The adder has a modified tree architecture using Load Distribution Method and has 6 logic stages.

A.R. SATANOVA 1, D.R. KAIDAROVA E.K. KUKUBASSOV R.O. BOLATBEKOVA 2, O.O. BERTLEUOV D.B. KALDYBEKOV 1 1. «Kazakh Institute of Oncology and Radiology» JSC, Almaty, the Republic Kazakhstan; 2. Almaty Center, Kazakhstan DOI: 10.52532/2663-4864-2022-2-64-79-83 УДК: 618.146-006.6:615.371 Год: 2022 выпуск: 64 номер: 2 страницы: 79-83 Скачать PDF: Ключевые […]