Network-on-Chip (NoC) is a promising communication paradigm for multiprocessor system-on-chips. This communication paradigm has been inspired from the packet-based communication networks and aims at overcoming the performance and scalability problems of the shared buses in multi-core SoCs (System on Chips)(Benini & Mecheli, 2002). Although the concept of NoCs is inspired from the traditional in...

OBJECTIVE The integration of the Common Drug Review (CDR) was a substantial change for Canada's public drug plans. Detailed comparisons of time-to-listing and proportion of medications covered by the province of Alberta's drug plans within the context of the CDR process have not been rigorously conducted. METHODS New drugs approved by Health Canada were identified five years prior to the CDR'...

Recently Network-on-Chip (NoC) technique has been proposed as a promising solution for on-chip interconnection network. However, different interface specification of integrated components raises a considerable difficulty for adopting NoC techniques. In this paper, we present a generic architecture for network interface (NI) and associated wrappers for a networked processor array (NoC based mult...

The genome is composed not only of genes but also of several noncoding functional elements (NOCs/ncFE, here I use NOCs), such as transcriptional promoters, enhancers, replication origins, centromeres and telomeres. rDNA has both gene and NOC characteristics. Thus, the rDNA encodes ribosomal RNAs, components of the ribosomes, that account for approximately 80% of the total RNA in a cell. However...

In this article we present test and verification challenges for system chips that utilize on-chip networks. These SOCs and networks on a chip are introduced, where the NOC is exemplified by Philips’ ÆTHEREAL NOC architecture. We discuss existing test and verification methods for SOCs and NOCs, and show the particular advantages of using an NOC for both testing and verifying the network, and tes...

Network on Chip (NoC) architecture attempts to address different component level architectures with specific interconnection network topologies and routing techniques, some of the topologies are CLICHE, Folded Torus, BFT. Only one distance vector routing used for different topologies. The work has not done with one routing for (CLICHE, Folded Torus and BFT) topologies. In this project we propos...

In this paper, an improved floorplanning algorithm, named the floorplanning algorithm based on particle swarm optimization algorithm nesting simulated annealing to optimize the floorplans (PSO-SA-NoC), has been proposed with simulations conducted to verify this algorithm. The simulation results are compared with the original Simulated Annealing-NoC. The results show that the CPU’s process time ...

This study was designed to characterize the role of the newly described endogenous opioid nociceptin/orphanin FQ (NOC/oFQ) in reduced cerebral blood flow (CBF) observed after ischemia-reperfusion (I/R) and combined hypoxia and ischemia-reperfusion (H-I/R), as a function of time after onset of reperfusion in newborn pigs equipped with a closed cranial window. Global cerebral ischemia (20 min) wa...

Recent research has shown that Network on-chip (NoC) is superior to a bus in terms of power and area for given traffic throughput requirements. Consequently, NoC is expected to be the main interconnect infrastructure in future System on Chip (SoC) and chip multi-processor (CMP). Unlike off-chip networks, VLSI modules are only a few millimeters apart, hence the cost of off-network communication ...

Rarely has there been as challenging and exciting a time for research in computer architecture as now. While, the proverbial Moore’s law has consistently helped architects integrate more and more silicon transistors in a single die, device constraints of power, heat, and reliability has forced the computer industry to shift focus from single processor core performance to instantiating multiple ...