We propose a pipelined parallel multiplier in phase-mode logic. The multiplier can be composed of combinations of gates which are the basic devices ofthe phasemode logic. Experimental operations of the ICF gate and the Adder cell for the multiplier are reported. The proposed multiplier has a Wallace-tree structure comprising trees of carry save adders for the addition of partial products. This ...

Multiplier is one of the major arithmetic operations carried out in DSP applications. This paper presents a modified Booth multiplier based on adiabatic logic. It is composed of Booth encoder, multiplier containing partial product generators and 1-bit (half and full) adders and final adder. Booth multiplication allows for smaller, faster multiplication circuits through encoding the signed numbe...

This study examines the multiplier effects of the grain subsidy program in China, which is a large food self-sufficiency project that is implemented as a cash transfer program. Income multiplier effects have not been examined in the evaluation of the grain subsidy program although increasing the income of farmers is the original goal of this project. A large number of household-level observatio...

In this paper we propose a modified probabilistic estimation bias (PEB) formula for fixed-width radix-4 Booth multiplier. The modified PEB formula estimates the same compensation value as the existing PEB formula without rounding operation. A bias circuit based on modified PEB formula generates one less carry-bit and involves less logic resources than the existing PEB circuit. The partial produ...

Previous articleNext article FreeThe Conservation MultiplierBard HarstadBard Harstad Search for more articles by this author PDFPDF PLUS Add to favoritesDownload CitationTrack CitationsPermissionsReprints Share onFacebookTwitterLinkedInRedditEmail SectionsMoreDetailsFiguresReferencesCited Journal of Political Economy Just Accepted Article DOIhttps://doi.org/10.1086/723637 Views: 112Total views ...