Low frequency noise characterisation of 0.12 μm SOI CMOS technology was performed for Partially and Fully Depleted N-MOSFETs. Static performances are first presented, then we address the drain current fluctuations in both linear and saturation regimes. Taking into consideration the usually admitted 1/f noise models in MOS devices and their applicability in our case, we finally point out the enh...

SOI (silicon-on-insulator) technology suffers from a number of floating body effects, most notably parasitic bipolar and history effects. These are influenced by the rapidly increasing gate tunneling current caused by an ultra-thin gate oxide, even at scaled VDDs [8]. This paper analyzes these effects in detail and proposes a number of novel circuit styles to minimize them. Simulation results a...

An overview is presented of the hybrid AlGaInAs-silicon platform that enables wafer level integration of III-V optoelectronic devices with silicon photonic devices based on silicon-on-insulator (SOI). Wafer bonding AlGaInAs quantum wells to an SOI wafer allows large scale hybrid integration without any critical alignment steps. Discrete hybrid silicon optical amplifiers, lasers and photodetecto...

We propose and simulate the characteristics of optical filters based on subwavelength gratings. In particular, we demonstrate through numerical simulations the feasibility of implementing SWG Bragg gratings in silicon-on-insulator (SOI). We also propose SWG ring resonators in SOI and verify their operation using numerical simulations and experiments. The fabricated devices exhibit an extinction...

We have designed a high-efficiency broadband grating coupler for coupling between silicon-on-insulator (SOI) waveguides and optical fibers. The grating is only 13 microm long and 12 microm wide, and the size of the grooves is optimized numerically. For TE polarization the coupling loss to single-mode fiber is below 1 dB over a 35-nm wavelength range when using SOI with a two-pair bottom reflect...

We propose a novel substrate-bias control scheme for an FD-SOI SRAM that suppresses inter-die variability. The proposed circuits detect inter-die threshold-voltage variation automatically, and then maximize read/write margins of memory cells to supply the substrate bias. We confirmed that a 486-kb 6T SRAM operates at 0.42 V, in which an FS corner can be compared as much as 0.14 V or more. key w...

MEMS devices are typical systems where multiphysics simulations are unavoidable. In this work, we present possible applications of 3-D self-assembled SOI (Siliconon-Insulator) MEMS such as, for instance, thermal actuators and flow sensors. The numerical simulations of these microsystems are presented. Structural and thermal parts have to be strongly coupled for correctly describing the fabricat...

The design of a 32-bit dual-issue 4-way super scalar PowerPC fixed point unit microprocessor tool research, in addition to being used for the analysis and development of circuit design techniques in SOI. (PUMA) in a 0.18mm TSMC process is described. The architectural details of the PUMA system are described. The design considerations and the implementation details are elaborated. This processor...

The leakage loss due to TM-TE mode coupling of TM-like whispering gallery mode in silicon-on-insulator (SOI) thin-ridge disk resonators is investigated for the first time to the best of our knowledge. We show that the propagation losses of TM-like mode in thin-ridge SOI disk resonators are significantly impacted by the radius of the disk. This behavior is predicted by a simple phenomenological ...

Our recent results on the demonstration of on-chip mode-division multiplexing functionalities are reviewed, with a special emphasis on the feasibility of nonlinear all-optical signal processing on the silicon-on-insulator (SOI) platform. Mode-selective parametric processes are demonstrated in a 4-mm long SOI waveguide. OCIS codes: (130.3120) Integrated optics devices; (030.4070) Modes; (130.740...