Hybrid memory systems consisting of DRAM and Non-Volatile Memory are promising to persist data fast. The index design of existing key-value stores for hybrid memory fails to utilize its specific performance characteristics: fast writes in DRAM, slow writes in NVM, and similar reads in DRAM and NVM. This paper presents HiKV, a persistent key-value store with the central idea of constructing a hy...

Merging processors and memory into a single chip has the well-known benefits of allowing high-bandwidth and lowlatency communication between processor and memory, and reducing energy consumption. As a result, many different systems based on what has been called Processor In Memory (PIM) architectures have been proposed [14, 2, 6, 7, 9, 11, 12, 13, 15, 16, 18]. Recent advances in technology [3, ...

This paper analyzes the design trade-offs in architecting large-scale DRAM caches. Prior research, including the recent work from Loh and Hill, have organized DRAM caches similar to conventional caches. In this paper, we contend that some of the basic design decisions typically made for conventional caches (such as serialization of tag and data access, large associativity, and update of replace...

This paper describes a three-dimensional DRAM in which the floating body capacitance (FBC) of a fully depleted SOI (FD-SOI) device is used as a storage node. This 1T DRAM lends itself particularly well to a 3D waferto-wafer bonding process because of the absence of deep etched and filled trench capacitor structure, and the improved thickness control tolerance in wafer thinning. A novel three-ti...

Recently, a great deal of research has gone into reducing the gap in performance between processors and their memory systems. Techniques such as prefetching have been developed in order to hide the long latencies involved in retrieving data from oo-chip DRAM. However, applications with irregular access patterns generally see greatly reduced beneet from these techniques, and latencies are becomi...

While there have been several studies and proposals for energy conservation for CPUs and peripherals, energy optimization techniques for selective operating mode control of DRAMs have not been fully explored. It has been shown that as much as 90% of overall system energy (excluding I/O) is consumed by the DRAM modules, serving as a good candidate for energy optimizations. Further, DRAM technolo...

We propose to combine two quite powerful ideas that have recently appeared in the Markov chain Monte Carlo literature: adaptive Metropolis samplers and delayed rejection. The ergodicity of the resulting non–Markovian sampler is proved, and the efficiency of the combination is demonstrated with various examples. We present situations where the combination outperforms the original methods: adapta...

Die-stacked DRAM is one of the most promising memory architectures to satisfy high bandwidth and low latency needs of many computing systems. But, with technology scaling, all memory devices are expected to experience significant increase in single and multi-bit errors. 3D die-stacked DRAM will have the added burden of protecting against single through-siliconvia (TSV) failures, which translate...

− We implemented POPeye (Probe of Performance + eye), a system analysis simulator to evaluate DRAM performance in a personal computer environment. When running any real-life application programs such as Microsoft Office and Paint Shop Pro on Windows OS, POPeye simulates detailed transactions between a CPU and a memory system. Using this tool, we comparatively analyzed the performance of a DDR-S...

Many I/O-intensive High Performance Computing applications like Map Reduce and database systems are incorporating in-memory computing technology to overcome traditional storage bandwidth bottlenecks. The volatile nature of DRAM makes these systems vulnerable to system crashes. Software based Write Aside Persistence is presented that provides atomic durability and consistency for persistent, byt...