We propose a method for dual supply voltage digital design to reduce energy consumption without violating the given performance requirement. Although the basic idea of placing low voltage gates on non-critical paths is well known, a new two-step procedures does it so more efficiently. First, given a circuit and its nominal single supply voltage, we find a suitable value for a lower second suppl...

This paper presents the design of a low-power voltage reference, bias current and the supply voltage for a 9-bit fully differential ADC. The references, power supply circuits and the ADC are integrated in one circuit, i.e. chip. The proposed chip is implemented in the UMC 0.18 μm CMOS process and occupies 800×700 μm. The circuit supply voltage V DD is obtained from the external RF signal. When ...

In this paper, a new D-latch topology has been implemented in MOS Current Mode Logic (MCML) that works on lower supply voltage than the D-latch topology already implemented in MCML. The already implemented D-latch topology is called Traditional DLatch Topology and the new D-latch topology that works on lower voltage is called low-voltage D-Latch Topology. Power consumed by MCML circuit is direc...

The dual supply voltage (dual-VDD) scheme reduces the active power consumption without performance degradation by using two power supply rails. However, an increase in the delay due to the scaled-down supply voltage has made assigning the lower supply voltage (VDDL) more difficult in the conventional dual-VDD scheme. We propose a technique for the dual-VDD scheme employing the Active Body-biasi...

Linear AC power supplies can be replaced by their nonlinear switching counterparts due to the lower voltage drops and higher efficiency and power density of switching-mode inverters. Multilevel cascaded H-bridge (CHB) converters are the preferred inverter structure because of modular configuration, control, and protection. The output voltage quality in CHB converters depends on the number of ou...

The binary counter is a fundamental unit of computer operation. The goal of this project is to lower the supply voltage and find the optimal supply voltage which provided less power

We report an SRAM with a 90% reduction of activeleakage power achieved by controlling the supply voltage. In our design, the supply voltage of a selected row in the SRAM goes up to 1 V, while that in other memory cells that are not selected is kept at 0.3 V. This suppresses active leakage because of the drain-induced barrier lowering (DIBL) effect. To avoid unexpected flips in the memory cells,...

A conventional high power DC power supply systems consist of a three-phase diode rectifier followed by a high frequency converter to supply loads at regulated DC voltage. These rectifiers draw significant harmonic currents from the utility, resulting in poor input power factor. In this paper, a DC power supply based on dual-bridge matrix converter (DBMC) with reduced number of switches is p...

Bridging faults in CMOS circuits sometimes degrade the output voltage and time performance without altering the logic function. The traditional voltage testing models based on the normal power supply voltage do not accurately model this behavior. In this paper we develop a model of bridging faults that accounts for both the bridging resistance distribution and gate sensitization and propagation...