Fault-based side channel cryptanalysis is very effective against symmetric and asymmetric encryption algorithms. Although straightforward hardware and time redundancy based concurrent error detection (CED) architectures can be used to thwart such attacks, they entail significant overhead (either area or performance). In this paper we investigate two systematic approaches to low-cost, low-latenc...

Fault injection has become over the years one of the most dangerous threats for embedded devices such as smartcards. It is thus mandatory for any embedded system to implement efficient protections against this hazard. Among the various countermeasures suggested so far, the idea of infective computation seems fascinating, probably due to its aggressive strategy. Originally conceived to protect a...

we investigate buchbaum and eisenbud's construction of the second symmetric power $s_r(x)$ of a chain complex $x$ of modules over a commutative ring $r$. we state and prove a number of results from the folklore of the subject for which we know of no good direct references. we also provide several explicit computations and examples. we use this construction to prove the following ...

The AES (Advanced Encryption Standard) is an emerging private-key cryptographic system. Performance requirements in many applications, in particular in embedded systems like smart-cards, require a HW implementation of AES, for instance as a coprocessor or as a macrocell to be added to the embedded system. A HW implementation of such a cryptographic system requires in turn to consider the fault ...

Advanced Encryption Standard (AES) is the symmetric key standard for encryption and decryption. In this work, a 128-bit AES encryption and decryption using Rijndael Algorithm is designed and synthesized using verilog code. The fault detection scheme for their hardware implementation plays an important role in making the AES robust to the internal and malicious faults. In the proposed AES, a com...

There is recently an interest in test generation for reversible circuits, but nothing has been published about fault localization in such circuits. The paper deals with fault localization for binary permutative reversible circuits. We concentrate on functional test based fault localization, and we generate an adaptive tree that depicts those faults that can be detected and localized. A striking...

The number of processors embedded in high performance computing platforms is growing daily to solve larger and more complex problems. The logical network topologies must also support the high degree of scalability in dynamic environments. This paper presents a scalable and fault tolerant topology called binomial graph (BMG). BMG provides desirable topological properties in terms of both scalabi...

We describe an extended fault model for Byzantine Agreement due to Schmid and Weiss. The new fault model extends the previous “hybrid” fault model of Thambidurai and Park by the addition of omission-faulty nodes, and by the introduction of link faults. We formally verify the Hybrid Oral Messages Algorithm (OMH) under this new fault model. Our formal verification improves the analysis of Schmid ...

We provide a first security evaluation of LPN-based implementations against fault attacks. Our main result is to show that such implementations inherently have good features to resist these attacks. First, some prominent fault models (e.g. where an adversary flips bits in an implementation) are ineffective against LPN. Second, attacks taking advantage of more advanced fault models (e.g. where a...

Figure 2.16: Models, seismograms and maximum amplitude distributions for two models with a fault widening towards the surface and a low velocity layer on top.. Figure 2.17: Selected seismograms, amplitude spectra and envelopes for the two models with a fault widening towards the surface and a low velocity layer on top .. Figure 4.10: Seismogram comparison of synthetics calculated with the refle...