A rapid growth in semiconductor technology and increasing demand for portable devices powered up by battery has led the manufacturers to scale down the feature size, resulting reduced threshold voltage and thereby enabling integration of extremely complex functionality on a single chip. In CMOS circuits, increased sub-threshold leakage current refers static power dissipation is the result of lo...

In this paper, we suggest that the dynamic power dissipation of a circuit can be used to detect faults in it. The change in dissipation caused by a fault can be maximized by applying speciic test vectors. For example circuits, we show that the power dissipation can be used to detect faults which do not aaect static power dissipation. We also discuss how faults may be detected with a frequency d...

Conventional MOS models for circuit simulation assume that the channel capacitances do not contribute to net power dissipation. Numerical integration of channel currents and instantaneous terminal voltages however shows the existence of higher order dissipating terms. To overcome these limitations, we present a self-consistent, first order, quasi-static power dissipation model that is able to p...

This paper presents a fast and low-power Static Random Access Memory (SRAM) design. SRAM are widely used in computer systems and many portable devices. Proposed SRAM is faster because of precharging at a desired voltage. For the most recent CMOS technologies leakage power dissipation has become a major concern. According to the International Technology Roadmap for Semiconductors (ITRS), leakage...

The storage for speculative values in superscalar processors is one of the main sources of complexity and power dissipation. In this paper, we present a novel technique to reduce register requirements as well as their dynamic and static power dissipation that is based on delaying the dispatch of instructions while minimizing its impact on performance. The proposed technique outperforms previous...

We present a formula of short-circuit power dissipation for static CMOS logic gates. By representing shortcircuit current by a piece-wise linear function and considering a current owing from input node to output node through gate capacitances, the accuracy is improved signi cantly. The error of our formula in a CMOS inverter is less than 15% from circuit simulation in many cases of our experime...

The present study evaluates four designs of XOR using our previously reported two-phase clocked adiabatic static CMOS logic (2PASCL) circuit techniques. 2PASCL XOR, which demonstrates the lowest power dissipation, is used for a 4ˆ4-bit array 2PASCL multiplier. Based on simulation results obtained using 0.18 —m standard CMOS technology, at transition frequencies of 1 to 100 MHz, the 4ˆ4-bit arra...

A new current-source control technique is proposed to design a low-power high-speed multiplevalued current-mode (MVCM) integrated circuit in a low supply voltage. The use of a di erential logic circuit (DLC) with a pair of dual-rail inputs makes the input voltage swing small, which results in a high driving capability at a lower supply voltage, while having large static power dissipation. In th...

This paper presents a broadband high operating frequency divide-by-2 frequency divider. This divider uses sourcecoupled logic (SCL) with two static loading master-slave D latches which achieves high input operating frequency, high input sensitivity and low power dissipation. This divider can work from 8GHz~ 27GHz and the input power is -40dBm@18GHz. The chip area is 735μm×480μm with only 4.6mW ...

Power dissipation is an increasing concern in VLSI circuits. New logic circuits have been developed to meet these power requirements. Power dissipation can be minimized by using various adiabatic logic circuits. In this paper an Adder circuit has been proposed based on 2PASCL and ECRL logic and then compared with Positive Feedback Adiabatic Logic(PFAL), Two-Phase Adiabatic Static Clocked Logic(...