–Cache is fastest memory which is played vital role in the present trend.Cache is achieved by SRAM. The scaling of CMOS technology has significant impact on SRAM cell -random fluctuation of electrical characteristics and substantial leakage current. In this paper we proposed dynamic column based power supply 8T SRAM cell to improve the read stability and low leakage. In this paper we compare th...

This paper proposes a novel adiabatic static random access memory (SRAM) using memristor. The proposed SRAM which is a sinusoidal driving consists of one NMOS transistor and one memristor (i.e. 1T1M type). The proposed SRAM also is driven by an optimal voltage resulting in a decrease of energy dissipation. From SPICE simulation results, we show that the energy dissipation of proposed 1T1M-SRAM ...

A SRAM cell must meet requirements for operation in submicron/nano ranges. The scaling of CMOS technology has significant impact on SRAM cell -random fluctuation of electrical characteristics and substantial leakage current. In this paper we present dynamic column based power supply 8T SRAM cell and comparing the proposed SRAM cell with respect to conventional SRAM 6T in various aspects. To ver...

One of the most challenging issues in wireless sensor networks is extension of the overall network lifetime. Data aggregation is one promising solution because it reduces the amount of network traffic by eliminating redundant data. In order to aggregate data, each sensor node must temporarily store received data, which requires a specific amount of memory. Most sensor nodes use static random ac...

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SRAM occupies two-third area of VLSI chips, therefore it dominates the total power consumption. To enhance the performance of these chips, SRAM cell should meet the requirement of lesser power consumption. This paper presents a new 8T SRAM cell that is efficient in Dynamic power consumption in Write mode and Leakage power consumption when compared with referred 9T SRAM cell and standard 6T SRAM...

In this paper, the authors propose a novel static random access memory (SRAM) that employs the adiabatic logic principle. To reduce energy dissipation, the proposed adiabatic SRAM is driven by two trapezoidal-wave pulses. The cell structure of the proposed SRAM has two high-value resistors based on a p-type metal-oxide semiconductor transistor, a cross-coupled n-type metal-oxide semiconductor (...

SRAM is a semiconductor memory cell. In this paper, a 10T SRAM cell is designed by using cadence virtuoso tool in 180nm CMOS technology. Its performance characteristics such as power, delay, and power delay product are analysed. 10T SRAM cell is basically 6T SRAM cell with 4 extra transistors. In this 10T SRAM cell, additional read circuitry is attached to avoid flipping of cell. The power diss...

We propose a fault-injection system (FIS) that can inject faults such as read/write margin failures and soft errors into a SRAM environment. The fault case generator (FCG) generates time-series SRAM failures in 7T/14T or 6T SRAM, and the proposed device model and fault-injection flow are applicable for system-level verification. For evaluation, an abnormal termination rate in vehicle engine con...

In modern digital architectures, more and more emphasis has been laid on increasing the number of SRAMs in a SoC. However, with the increase in the number of SRAMs, the power requirement also increases, which is not desired. This calls for an urgent need for an SRAM with low dynamic and static power consumption and stability at the same time. The design and simulation work for 6T-SRAM, NC-SRAM,...