The silicon-on-insulator (SOI) material system is today widely recognized as one of the most important platforms for the development of photonic components. This is mainly due to the fact that the mass fabrication techniques of the CMOS technology can be used for the fabrication of these SOI components. However, using silicon for photonic components has significant downsides. For example, it is...

Smart power ICs, which monolithically integrate low-loss power devices and control circuitry, have attracted much attention in a wide variety of applications [1], [2]. Commonly used smart power devices are the LDMOS and LIGBT implemented in bulk silicon or SOI (Silicon on Insulator). One of the key issues in the realization of such ‘smart power’ technology is the isolation of power devices and ...

In this paper an introduction to substrate noise in silicon on insulator (SOI) is given. Differences between substrate noise coupling in conventional bulk CMOS and SOI CMOS are discussed and analyzed by simulations. The efficiency of common substrate noise reduction methods are also analyzed. Simulation results show that the advantage of the substrate isolation in SOI is only valid up to a freq...

SOI technology for state of the art CMOS technology is rapidly approaching maturity. PD-SOI device design has the advantage of easier manufacturing but requires more sophisticated device and circuit design to reduce the effects of the floating-body. FD-SOI device design potentially has the advantage of no floating-body effects but requires very thin silicon films making manufacturing more chall...

Double-gate fully depleted (DGFD) SOI circuits are regarded as the next generation VLSI circuits. This paper investigates the impact of scaling on the demand and challenges of DGFD SOI circuit design for low power and high performance. We study how the added back-gate capacitance affects circuit power and performance; how to tradeoff the enhanced short-channel effect immunity with the added bac...

In this paper, we present: 1) design of a single-rail energy-efficient 64-b Han–Carlson ALU, operating at 482 ps in 1.5 V, 0.18m bulk CMOS; 2) direct port of this ALU to 0.18m partially depleted SOI process; 3) SOI-optimal redesign of the ALU using a novel deep-stack quaternary-tree architecture; 4) margining for max-delay pushout due to reverse body bias in SOI designs; and 5) performance scal...

Silicon-on-insulator ~SOI! has proven to be a viable alternative to traditional bulk silicon for fabrication of complementary metal–oxide–semiconductor devices. However, a number of unusual phenomena with regards to diffusion and segregation of dopants in SOI have yet to be explained. In the present study, SOITEC wafers were thinned to 700 and 1600 Å using oxidation and etching. Ion implantatio...

Silicon substrate losses and non-linearities were the limiting characteristics of Si-based MOSFET technologies to provide low-power and low-cost solutions to the mobile RF device market. Thanks to the trap-rich Silicon-on-Insulator (SOI) substrate invented at UCL and developed in collaboration with the French company SOITEC, RF SOI is becoming a mainstream technology which is implemented in all...