Abstract-Two new algorithms for performing arithmetic coding without employing multiplication are presented. The first algorithm, suitable for an alphabet of arbitrary size, reduces the worst case normalized excess length to under 0.8% vs 1.911% for the previously known best method of Chevion et a/. The second algorithm, suitable only for alphabets of less than 12 symbols, allows even greater r...

Noise eeects such as power supply and crosstalk noise can signiicantly impact the performance of deep submicron designs. Existing timing analysis tecniques cannot capture the eeects of noise on the signal/cell delays. This is because these delay eeects are highly input pattern dependent. Therefore, the predicted circuit performance might not reeect the worst-case circuit delay. In this paper, w...

The deep submicron semiconductor technologies will make the worst-case design impossible, since they can not provide design margins that it requires. Research directions should go to typical-case design methodologies, where designers are focusing on typical cases rather than worrying about very rare worst cases. They enable to eliminate design margins as well as to tolerate parameter variations...

In this paper I discuss the relationship between model, theories, and laws in the practice of experimental scale modeling. The methodology of experimental scale modeling, also known as physical similarity, differs markedly from that of other kinds of models in ways that are important to issues in philoso-phy of science. In this paper, I examine how scale models are used in making inferences. Th...

A novel architecture is presented for combining rule-based and case-based reasoning. The central idea is to apply the rules to a target problem to get a rst approximation to the answer; but if the problem is judged to be compellingly similar to a known exception of the rules in any aspect of its behavior, then that aspect is modelled after the exception rather than the rules. The architecture i...

in data envelopment analyze (dea) the scale efficiency in the input-oriented ccr model is less than or equal to the scale efficiency in dea based on the fractional analysis (dea-r). also, the scale efficiency in case of multiple inputs and one output and vice versa the scale efficiencies are equal in dea and dea-r. in this paper, first, dea-r model with weight restrictions when there is relativ...

Qualitatively comparing the shapes of time histories to validate experiments with computational simulations is a common technique in both general computational mechanics as well as computational roadside safety. Qualitative comparisons, however, are subjective and open to interpretation. A variety of quantitative metrics are available for comparing time history data as well but developing accep...

Fujitsu has developed a technique that can automatically prepare test scenarios/ data, run the tests, and check the results based on a formal description of the application’s external specifications. This eliminates problems that can arise in conventional test methods, such as failure to consider all possible test cases or data values, the existence of too many test cases for exhaustive testing...

Floor-planning is a fundamental step in VLSI chip design. Based upon the concept of orderly spanning trees, we present a simple O(n)-time algorithm to construct a floorplan for any n-node plane triangulation. In comparison with previous floor-planning algorithms in the literature, our solution is not only simpler in the algorithm itself, but also produces floor-plans which require fewer module ...

We present a framework for content based retrieval (CBR) of remotely sensed imagery. The main focus of our research is the segmentation step in CBR. A bank of gabor filters is used to extract regions of homogeneous texture. These filter responses are utilized in a multiscale clustering technique to yield the final segmentation. Novel area morphological filters are utilized for the purpose of sc...