increasing the number of cores integrated on a chip and the problems of system on chips caused to emerge networks on chips. nocs have features such as scalability and high performance. nocs architecture provides communication infrastructure and in this way, the blocks were produced that their communication with each other made noc. due to increasing number of cores, the placement of the cores i...

we design and simulate a five-port optical router, which is composed of twenty mach-zehnder-based switching elements and twelve waveguide crossings for use in integrated photonic interconnection networks. we simulated and analyzed the operation of the proposed optical router from the aspects of insertion loss, power budget, q-factor and the minimum bit error ratio by use of optisystem simulator...

Switch Allocation (SA) holds a critical stage in Network-on-Chip (NoC) routers, its performance gets affected adversely due to Head-of-Line (HoL) blocking. In traditionally used Input-Queued Routers (IQR), packets are arranged particular order each Virtual Channel (VC). This implementation is vulnerable HoL blocking, as the switch allocator can allocate only those which available at head VC. th...

One aspect of network mobility support is the assignment of a prefix or prefixes to a mobile router for use on the links in the mobile network. This document specifies how DHCPv6 prefix delegation can be used for this configuration task. The mobile router plays the role of requesting router, while the home agent assumes the role of delegating router. When the mobile router is outside its home n...

Due to the increasing growth of processing cores in complex computational systems, all the connection converted bottleneck for all systems. With the protection of progressing and constructing complex photonic connection on chip, optical data transmission is the best choice for replacing with electrical interconnection for the reason of gathering connection with a high bandwidth and insertion lo...

In this paper, we present an efficient multilayer general area router, named V4, for MCM and dense PCB designs. The unique feature of the V4 router is that it uses no more than four vias to route every net and yet produces high quality routing solutions. A number of combinatorial optimization techniques are used in the V4 router to produce high quality routing solutions in polynomial time. As a...