As the scale of integration keeps growing, more and more sophisticated signal processing systems are being implemented on a VLSI chip. These signal processing applications not only demand great computation capacity but also consume considerable amounts of energy. While performance and area remain to be two major design goals, power consumption has become a critical concern in today’s VLSI syste...

This paper presents radix-4 and radix-8 Booth encoded modular multipliers over general Fp based on interleaved multiplication algorithm. An existing bit serial interleaved multiplication algorithm is modified using radix-4, radix-8 and Booth recoding techniques. The modified radix-4 and radix-8 versions of interleaved multiplication result in 50% and 75% reduction in required number of clock cy...

This paper describes implementation of radix-4 Modified Booth Multiplier and this implementation is compared with Radix-2 Booth Multiplier. Modified Booth’s algorithm employs both addition and subtraction and also treats positive and negative operands uniformly. No special actions are required for negative numbers. In this Paper, we investigate the method of implementing the Parallel MAC with t...

We present a new architecture for signed multiplication which maintains the pure form of an array multiplier, exhibiting a much lower overhead than the Booth architecture. This architecture is extended for radix-2 encoding, which leads to a reduction of the number of partial lines, enabling a significant improvement in performance and power consumption. The flexibility of our architecture allow...

A highly-scaleable FIR architecture based on the radix-4 Booth algorithm has been designed with scaleable dynamic ranges of input data and filter coefficients. The radix-4 Booth algorithm is demonstrated to have a lower hardware complexity and a fair throughput rate than the other radix approaches. In order to achieve scaleability, the configurable-connection function between latches of input d...

This paper introducing a novel technique called as redundant binary booth algorithm. The redundant binary in the design of high-speed digital multipliers is beneficial due to its high modularity and carry-free addition. Generally, in a high radix modified Booth encoding algorithm the partial products are reduced in multiplication process. But it yields complexity in producing in generation of h...

The Booth multiplication algorithm produces incorrect results for some word sizes, when it is extended for higher radix, fixed-point multiplication. We present a modification of the Booth algorithm that produces correct results when the radix is any power of 2 and the multipliers are of any size.

The MAC provides high speed multiplication with accumulative addition. In this paper, we study the various parallel MAC architectures and then implement a design of parallel MAC based on some booth encodings such as radix-4 booth encoder and some final adders such as CLA, Kogge stone adder and then compare their performance characteristics. The one most effective way to increase the speed of a ...

In this paper, we introduce an architecture of pre-encoded multipliers for Digital Signal Processing applications based on off-line encoding of coefficients. To this extend, the Non-Redundant radix-4 Signed-Digit (NR4SD) encoding technique, which uses the digit values {-1, 0, +1, +2} or {-2,-1,0,+1}, is proposed leading to a multiplier design with less complex partial products implementation. E...