this paper presents a new mathematical model for a hybrid flow shop scheduling problem with multiprocessor tasks in which sequence dependent set up times and preemption are considered. the objective is to minimize the weighted sum of makespan and maximum tardiness. three meta-heuristic methods based on genetic algorithm (ga), imperialist competitive algorithm (ica) and a hybrid approach of ga a...

This paper proposes balancing scheduling effort more evenly between the compiler and the processor, by introducing dynamically scheduled Very Long Instruction Word (VLIW) instructions. Dynamically Instruction Scheduled VLIW (DISVLIW) processor is aimed specifically at dynamic scheduling VLIW instructions with dependency information. The DISVLIW processor dynamically schedules each instruction w...

compiler to exploit high ILP using EPIC techniques [SI. M-64 processor architecture implementing this concept is the processor architecture where the compiler is responsible for This paper evaluates performance of the Dynamically efficiently exploiting the available ILP and keeps the Inslructian Sch&led KlW P I S w pmcersor mhitechnz. executions busy. Instead of the merits, the IA-64 processor ...

In this paper, we present an approach to determine scheduling functions suitable for the design of processor arrays. The considered scheduling functions support a followed LSGP-partitioning of the processor array by allowing to execute the tasks of processors of the full-size array mapped into one processor of the partitioned processor array in an arbitrary order. Several constraints are derive...