In this paper two ultra high speed carbon nanotube FullAdder cells are presented. First design uses two transistors, two resistors and seven capacitors and the second one uses four transistors and seven capacitors. The first design is faster and the second one consumes less power. Simulation results illustrate significant improvement in terms of speed and Power-Delay Product (PDP).

This paper presents power analysis of the full adder cells reported as having a low PDP (Power Delay Product), by means of speed, power consumption and area. These full adders were designed upon various logic styles to derive the sum and carry outputs. Two new high-speed and low-power full adder cells designed with an alternative internal logic structure and pass-transistor logic styles that le...

   Nowadays, the portable multimedia electronic devices, which employ signal-processing modules, require power aware structures more than ever. For the applications associating with human senses, approximate arithmetic circuits can be considered to improve performance and power efficiency. On the other hand, scaling has led to some limitations in performance of nanoscale circuits. According...

We report a 72.8 GHz fully static frequency divider in AIInAs/InGaAs HBT IC technology. The CML divider operates with a 350 mV logic swing at less than OdBm input power up to a maximum clock rate of 63 GHz and requires 8.6 dBm of input power at the maximum clock rate of 72.8GHz. Power dissipation per flip-flop is 55mW with a 3.1V power supply. To our knowledge this is the highest frequency of o...

full adder cell is often placed in the critical path of other circuits. therefore it plays an important role in determining the entire performance of digital system. moreover, portable electronic systems rely on battery and low-power design is another concern. in conclusion it is a vital task to design high-performance and low-power full adder cells. since delay opposes against power consumptio...

In this paper, the performance of a CNT-JLTFET under different values of torsional strains of 0, 3, and 5 degrees has been investigated. Simulation has been carried out using non-equilibrium Green’s function (NEGF) formalism in the mode-space approach and in the ballistic limit. The simulation results indicate that, under torsional strain, an increase occurs in the energy band-gap, and thus the...

this paper proposes a buffer circuit for footed domino logic circuit. It minimizes redundant switching at the output node. This circuit prevents propagation of precharge pulse to the output node during precharge phase which saves power consumption. We have calculated the power consumption, delay and power delay product of proposed circuits and compared the results with existing domino circuit f...

This paper describes a transistor sizing methodology for both analog and digital CMOS circuits. Various techniques are used for power optimization in CMOS VLSI circuits. Transistor sizing is one of the important techniques for the determination of circuit performance. The aim of the power optimization is to minimize the power and power-delay product or the energy consumption of the circuit. Thu...

ARTICLE INFO In digital signal processing we use delayed least mean square adaptive filter is used to find the lower adaptation delay and area –delay-power efficient architecture which uses the novel partial product generator. The proposed system optimizes the balanced pipelining across the time consuming combinational blocks of the structure. The objective is to reduce the number of pipelining...