Circuit simulation model for advanced SOI-MOSFETs has been developed by solving Poisson’s equation consistently. It is successfully proven that, as a result of solving the Poisson’s equation considering its device structure, our model is applicable for various variations of SOI-MOSFETs such as partially depleted (PD), fully depleted (FD) and dynamically depleted SOI-MOSFETs, which is the indisp...

We present a novel half-select disturb free transistor SRAM cell. The cell is 6T based and utilizes decoupling logic. It employs gated inverter SRAM cells to decouple the column select read disturb scenario in half-selected columns which is one of the impediments to lowering cell voltage. Furthermore, “false read” before write operation, common to conventional 6T designs due to bit-select and w...

In this article, a novel concept is introduced to improve the Radio Frequency (RF) linearity of Partially-Depleted (PD) Silicon-On-Insulator (SOI) MOSFET circuits. The transition due to the non-zero body resistance (RBody) in output conductance of PD SOI devices leads to linearity degradation. A relation for RBody is defined to eliminate the transition and a method to obtain transition-free cir...

SOI technology for state of the art CMOS technology is rapidly approaching maturity. PD-SOI device design has the advantage of easier manufacturing but requires more sophisticated device and circuit design to reduce the effects of the floating-body. FD-SOI device design potentially has the advantage of no floating-body effects but requires very thin silicon films making manufacturing more chall...

For the first time, we report the combined application of a SiGe source and a delta-doped + region in a PD SOI MOSFET to minimize the impact of floating body effect on both the drain breakdown voltage and the single transistor latch. Our results demonstrate that the proposed SOI structure exhibits as large as 200% improvement in the breakdown voltage and is completely immune to single transisto...

We present a novel half-select disturb free transistor SRAM cell. The cell is 6T based and utilizes decoupling logic. It employs gated inverter SRAM cells to decouple the column select read disturb scenario in half-selected columns which is one of the impediments to lowering cell voltage. Furthermore, “false read” before write operation, common to conventional 6T designs due to bit-select and w...

SOI (silicon-on-insulator) technology suffers from a number of floating body effects, most notably parasitic bipolar and history effects. These are influenced by the rapidly increasing gate tunneling current caused by an ultra-thin gate oxide, even at scaled VDDs [8]. This paper analyzes these effects in detail and proposes a number of novel circuit styles to minimize them. Simulation results a...

The recent progress of BSIM (Berkeley Short-channel IGFET Model) SPICE models extended for SOI transistors are reviewed. The models cover partially depleted (PD), fully depleted (FD) and dynamic depletion (FD) (automatically transition between PD and FD). The key concept of dynamic depletion will be discussed.

This paper describes applications of Silicon on Insulator (SOI) technology to high performance onchip memories (e.g. SRAMs and register files etc.).The primary focuses are on the important and unique issues in SOI technology such as performance gain, history effect, power reduction, pulsewidth control and self-heating. The effects on the interconnect performance and reliability are also discuss...